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1. 发明申请

US20130100734A1 APPARATUS AND METHOD FOR TRIMMING REFERENCE CELL IN SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于在半导体存储器件中修剪参考电池的装置和方法
公开(公告)号：US20130100734A1
公开(公告)日：2013-04-25
申请号：US13276779
申请日：2011-10-19
申请人： Chung-Shan KUO
发明人： Chung-Shan KUO
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/28
摘要： A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of a precision resistor disposed outside the semiconductor memory device; comparing the reference current with the first current; comparing the reference current with the second current; programming the reference cell if the value of the reference current is greater than that of the first current; and erasing the reference cell if the value of the reference current is less than that of the second current. The value of the second current is less than that of the first current.
摘要翻译：一种在半导体存储器件中修整参考单元的方法包括以下步骤：基于施加到参考单元的偏置电压产生参考电流; 基于控制电压的值和设置在半导体存储器件外部的精密电阻器的电阻产生第一电流和第二电流; 将参考电流与第一电流进行比较; 将参考电流与第二电流进行比较; 如果参考电流的值大于第一个电流的值，则编程参考单元; 并且如果参考电流的值小于第二电流的值，则擦除参考单元。第二电流的值小于第一电流的值。

2. 发明申请

US20120287717A1 FLASH MEMORY DEVICE AND ASSOCIATED CHARGE PUMP CIRCUIT 有权
标题翻译：闪存存储器和相关的充电泵电路
公开(公告)号：US20120287717A1
公开(公告)日：2012-11-15
申请号：US13105467
申请日：2011-05-11
申请人： Chung Shan Kuo
发明人： Chung Shan Kuo
IPC分类号： G11C11/21 , G05F3/02
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/0077 , H02M2001/008 , H02M2003/077
摘要： A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second booster group receives the supply voltage and generates the first output voltage or a second output voltage according to the detecting signal. The second booster group is composed of a plurality of booster sets connected in parallel, wherein each booster set comprises a plurality of charge pump stages and a plurality of switch units. The number of serially-connected charge pump stages of each booster set in the second booster group is controlled by the plurality of switch units according to the stable voltage levels of the first and second output voltages.
摘要翻译：电荷泵电路包括第一升压器组，第二升压组和检测电路。第一升压器组接收电源电压并产生第一输出电压。检测电路根据第一输出电压的电压电平产生检测信号。第二升压组根据检测信号接收电源电压并产生第一输出电压或第二输出电压。第二升压组由并联连接的多个升压组构成，其中每个升压组包括多个电荷泵级和多个开关单元。根据第一和第二输出电压的稳定电压电平，由多个开关单元控制在第二升压组中设置的每个升压器的串联连接的电荷泵级数。

3. 发明授权

US07542352B1 Bit line precharge circuit 有权
标题翻译：位线预充电电路
公开(公告)号：US07542352B1
公开(公告)日：2009-06-02
申请号：US12208348
申请日：2008-09-11
申请人： Chung-Shan Kuo
发明人： Chung-Shan Kuo
IPC分类号： G11C16/06
CPC分类号： G11C16/24 , G11C16/28
摘要： A bit line precharge circuit is provided by the present invention. The bit line precharge circuit groups the precharge sub-circuits to share one drain bias controller. The drain bias controller has an inverter and a NMOS clamping transistor to form a negative feedback loop, to quickly precharge bit lines. When operating in read operation, only one drain bias controller is needed. Therefore, it can greatly save the layout area and operating power consumption without any extra dummy bit line or layout expansion.
摘要翻译：本发明提供位线预充电电路。位线预充电电路将预充电子电路组合以共享一个漏极偏置控制器。漏极偏置控制器具有反相器和NMOS钳位晶体管，以形成负反馈环路，以快速对位线进行预充电。在读操作中工作时，只需要一个漏极偏置控制器。因此，可以大大节省布局面积和工作功耗，无需任何额外的虚拟位线或布局扩展。

4. 发明申请

US20080144389A1 WORD LINE DRIVER DESIGN IN NOR FLASH MEMORY 有权
标题翻译： WORD线驱动器设计在NOR闪存中
公开(公告)号：US20080144389A1
公开(公告)日：2008-06-19
申请号：US11610573
申请日：2006-12-14
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/10
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
摘要翻译：一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一偏置端子

5. 发明授权

US08456922B2 Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage 有权
公开(公告)号：US08456922B2
公开(公告)日：2013-06-04
申请号：US13477431
申请日：2012-05-22
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

6. 发明授权

US07924610B2 Method for conducting over-erase correction 有权
标题翻译：进行过擦除校正的方法
公开(公告)号：US07924610B2
公开(公告)日：2011-04-12
申请号：US12350635
申请日：2009-01-08
申请人： Chung Zen Chen , Chung Shan Kuo , Tzeng Ju Hsue , Ching Tsann Leu
发明人： Chung Zen Chen , Chung Shan Kuo , Tzeng Ju Hsue , Ching Tsann Leu
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/3409
摘要： A method for conducting an over-erase correction describes the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a hot carrier HC soft program to correct over-erased cells if bit line leakage is found after the second erase and verification operation.
摘要翻译：进行过擦除校正的方法描述了进行第一擦除和验证操作的步骤; 在第一擦除和验证操作之后，如果发现位线泄漏，则使用FN软程序校正过擦除的单元; 进行第二次擦除和验证操作; 并且如果在第二擦除和验证操作之后发现位线泄漏，则使用热载波HC软程序校正过擦除的单元。

7. 发明申请

US20100172188A1 METHOD FOR CONDUCTING OVER-ERASE CORRECTION 有权
标题翻译：导致过度修正的方法
公开(公告)号：US20100172188A1
公开(公告)日：2010-07-08
申请号：US12350635
申请日：2009-01-08
申请人： CHUNG ZEN CHEN , CHUNG SHAN KUO , TZENG JU HSUE , CHING TSANN LEU
发明人： CHUNG ZEN CHEN , CHUNG SHAN KUO , TZENG JU HSUE , CHING TSANN LEU
IPC分类号： G11C16/06
CPC分类号： G11C16/3404 , G11C16/3409
摘要： A method for conducting an over-erase correction comprises the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a hot carrier HC soft program to correct over-erased cells if bit line leakage is found after the second erase and verification operation.
摘要翻译：进行过擦除校正的方法包括以下步骤：进行第一擦除和验证操作; 在第一擦除和验证操作之后，如果发现位线泄漏，则使用FN软程序校正过擦除的单元; 进行第二次擦除和验证操作; 并且如果在第二擦除和验证操作之后发现位线泄漏，则使用热载波HC软程序校正过擦除的单元。

8. 发明授权

US07443230B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07443230B2
公开(公告)日：2008-10-28
申请号：US11463597
申请日：2006-08-10
申请人： Chung-Zen Chen , Chung-Shan Kuo , Yang-Chieh Lin
发明人： Chung-Zen Chen , Chung-Shan Kuo , Yang-Chieh Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.
摘要翻译：提供了包括多个受控电荷泵（CP），多个不受控制的CP，多个控制单元和输出单元的电荷泵电路。每个受控CP确定是否通过控制信号向节点提供费用，并且每个不受控制的CP不断向节点提供费用。节点处的节点电压越高，对节点不提供电荷的受控CP越多，以抑制节点的电压。此外，输出单元通过负反馈调节并输出根据节点电压的输出电压。

9. 发明授权

US08391069B2 Programming method for nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的编程方法
公开(公告)号：US08391069B2
公开(公告)日：2013-03-05
申请号：US13105539
申请日：2011-05-11
申请人： Chung Shan Kuo , Zi Qiang Ku
发明人： Chung Shan Kuo , Zi Qiang Ku
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/10 , G11C16/3454
摘要： A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: sequentially performing a plurality of divide-by-2 operations on the plurality of memory cells; generating a plurality of reduced groups from the memory cells after each of the divide-by-2 operations is performed; sequentially programming the memory cells of each reduced group; generating a final group after a final divide-by-2 operation is performed; programming the memory cells of the final group; and verifying whether the memory cells of the final group are completely programmed. The memory cells of the final group are composed of all the memory cells of the nonvolatile semiconductor memory device and the verifying step is only performed after the step of programming the memory cells of the final group.
摘要翻译：一种用于编程非易失性半导体存储器件的多个存储单元的方法包括以下步骤：在多个存储器单元上顺序执行多个除以2的运算; 在执行每次分割2操作之后，从存储器单元生成多个缩减组; 对每个还原组的存储单元进行顺序编程; 在执行最后的除2操作之后产生最终组; 编程最后一组的记忆单元; 并验证最终组的存储单元是否被完全编程。最终组的存储单元由非易失性半导体存储器件的所有存储单元构成，并且验证步骤仅在编程最终组的存储单元的步骤之后执行。

10. 发明授权

US08848476B2 Flash memory device and associated charge pump circuit 有权
标题翻译：闪存器件和相关的电荷泵电路
公开(公告)号：US08848476B2
公开(公告)日：2014-09-30
申请号：US13105467
申请日：2011-05-11
申请人： Chung Shan Kuo
发明人： Chung Shan Kuo
IPC分类号： G11C5/14 , H02M3/07 , H02M1/00
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/0077 , H02M2001/008 , H02M2003/077
摘要： A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second booster group receives the supply voltage and generates the first output voltage or a second output voltage according to the detecting signal. The second booster group is composed of a plurality of booster sets connected in parallel, wherein each booster set comprises a plurality of charge pump stages and a plurality of switch units. The number of serially-connected charge pump stages of each booster set in the second booster group is controlled by the plurality of switch units according to the stable voltage levels of the first and second output voltages.
摘要翻译：电荷泵电路包括第一升压器组，第二升压组和检测电路。第一升压器组接收电源电压并产生第一输出电压。检测电路根据第一输出电压的电压电平产生检测信号。第二升压组根据检测信号接收电源电压并产生第一输出电压或第二输出电压。第二升压组由并联连接的多个升压组构成，其中每个升压组包括多个电荷泵级和多个开关单元。根据第一和第二输出电压的稳定电压电平，由多个开关单元控制在第二升压组中设置的每个升压器的串联连接的电荷泵级数。

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