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1. 发明授权

US08456922B2 Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage 有权
公开(公告)号：US08456922B2
公开(公告)日：2013-06-04
申请号：US13477431
申请日：2012-05-22
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

2. 发明授权

US07443230B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07443230B2
公开(公告)日：2008-10-28
申请号：US11463597
申请日：2006-08-10
申请人： Chung-Zen Chen , Chung-Shan Kuo , Yang-Chieh Lin
发明人： Chung-Zen Chen , Chung-Shan Kuo , Yang-Chieh Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.
摘要翻译：提供了包括多个受控电荷泵（CP），多个不受控制的CP，多个控制单元和输出单元的电荷泵电路。每个受控CP确定是否通过控制信号向节点提供费用，并且每个不受控制的CP不断向节点提供费用。节点处的节点电压越高，对节点不提供电荷的受控CP越多，以抑制节点的电压。此外，输出单元通过负反馈调节并输出根据节点电压的输出电压。

3. 发明授权

US07277329B2 Erase method to reduce erase time and to prevent over-erase 有权
标题翻译：擦除方法可以减少擦除时间并防止过度擦除
公开(公告)号：US07277329B2
公开(公告)日：2007-10-02
申请号：US11297085
申请日：2005-12-08
申请人： Chung-Zen Chen , Chung-Shan Kuo
发明人： Chung-Zen Chen , Chung-Shan Kuo
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/16 , G11C16/3472
摘要： An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.
摘要翻译：在布置在多个扇区中的闪存单元阵列中使用的擦除方法为每个扇区提供擦除标志。要擦除的扇区的擦除标志被设置为第一值。存储器单元从第一扇区到其标志被设置为第一值的最后扇区以及从第一地址到最后地址的每个扇区被顺序地验证。当验证失败并且相同小区验证的数量小于预定数量时，该方法应用擦除脉冲并再次在相同存储器地址处验证存储器调用。当验证失败并且同一单元验证的数量达到预定数量时，验证标志被设置为第一值的剩余扇区。当要擦除的扇区的每个存储单元通过验证时，扇区的擦除标志被设置为第二值。当要擦除的每个扇区的标志被设置为第二值时，擦除操作终止。

4. 发明授权

US07542352B1 Bit line precharge circuit 有权
标题翻译：位线预充电电路
公开(公告)号：US07542352B1
公开(公告)日：2009-06-02
申请号：US12208348
申请日：2008-09-11
申请人： Chung-Shan Kuo
发明人： Chung-Shan Kuo
IPC分类号： G11C16/06
CPC分类号： G11C16/24 , G11C16/28
摘要： A bit line precharge circuit is provided by the present invention. The bit line precharge circuit groups the precharge sub-circuits to share one drain bias controller. The drain bias controller has an inverter and a NMOS clamping transistor to form a negative feedback loop, to quickly precharge bit lines. When operating in read operation, only one drain bias controller is needed. Therefore, it can greatly save the layout area and operating power consumption without any extra dummy bit line or layout expansion.
摘要翻译：本发明提供位线预充电电路。位线预充电电路将预充电子电路组合以共享一个漏极偏置控制器。漏极偏置控制器具有反相器和NMOS钳位晶体管，以形成负反馈环路，以快速对位线进行预充电。在读操作中工作时，只需要一个漏极偏置控制器。因此，可以大大节省布局面积和工作功耗，无需任何额外的虚拟位线或布局扩展。

5. 发明申请

US20080144389A1 WORD LINE DRIVER DESIGN IN NOR FLASH MEMORY 有权
标题翻译： WORD线驱动器设计在NOR闪存中
公开(公告)号：US20080144389A1
公开(公告)日：2008-06-19
申请号：US11610573
申请日：2006-12-14
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/10
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
摘要翻译：一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一偏置端子

6. 发明授权

US08693266B2 Apparatus and method for trimming reference cell in semiconductor memory device 有权
标题翻译：半导体存储器件中修整参考单元的装置和方法
公开(公告)号：US08693266B2
公开(公告)日：2014-04-08
申请号：US13276779
申请日：2011-10-19
申请人： Chung-Shan Kuo
发明人： Chung-Shan Kuo
IPC分类号： G11C7/14
CPC分类号： G11C16/10 , G11C16/28
摘要： A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of a precision resistor disposed outside the semiconductor memory device; comparing the reference current with the first current; comparing the reference current with the second current; programming the reference cell if the value of the reference current is greater than that of the first current; and erasing the reference cell if the value of the reference current is less than that of the second current. The value of the second current is less than that of the first current.
摘要翻译：一种在半导体存储器件中修整参考单元的方法包括以下步骤：基于施加到参考单元的偏置电压产生参考电流; 基于控制电压的值和设置在半导体存储器件外部的精密电阻器的电阻产生第一电流和第二电流; 将参考电流与第一电流进行比较; 将参考电流与第二电流进行比较; 如果参考电流的值大于第一个电流的值，则编程参考单元; 并且如果参考电流的值小于第二电流的值，则擦除参考单元。第二电流的值小于第一电流的值。

7. 发明申请

US20120230119A1 WORD LINE DRIVER IN FLASH MEMORY 有权
标题翻译： WASH LINE DRIVER IN FLASH MEMORY
公开(公告)号：US20120230119A1
公开(公告)日：2012-09-13
申请号：US13477431
申请日：2012-05-22
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/10
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
摘要翻译：一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一偏置端子

8. 发明授权

US08189396B2 Word line driver in a hierarchical NOR flash memory 有权
标题翻译：分级NOR闪存中的字线驱动程序
公开(公告)号：US08189396B2
公开(公告)日：2012-05-29
申请号：US11610573
申请日：2006-12-14
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/08
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
摘要翻译：一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一偏置端子

9. 发明申请

US20080036528A1 CHARGE PUMP CIRCUIT 有权
标题翻译：充电泵电路
公开(公告)号：US20080036528A1
公开(公告)日：2008-02-14
申请号：US11463597
申请日：2006-08-10
申请人： Chung-Zen Chen , Chung-Shan Kuo , Yang-Chieh Lin
发明人： Chung-Zen Chen , Chung-Shan Kuo , Yang-Chieh Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.
摘要翻译：提供了包括多个受控电荷泵（CP），多个不受控制的CP，多个控制单元和输出单元的电荷泵电路。每个受控CP确定是否通过控制信号向节点提供费用，并且每个不受控制的CP不断向节点提供费用。节点处的节点电压越高，对节点不提供电荷的受控CP越多，以抑制节点的电压。此外，输出单元通过负反馈调节并输出根据节点电压的输出电压。

10. 发明申请

US20070076465A1 Erase method to reduce erase time and to prevent over-erase 有权
公开(公告)号：US20070076465A1
公开(公告)日：2007-04-05
申请号：US11297085
申请日：2005-12-08
申请人： Chung-Zen Chen , Chung-Shan Kuo
发明人： Chung-Zen Chen , Chung-Shan Kuo
IPC分类号： G11C17/00
CPC分类号： G11C16/3468 , G11C16/16 , G11C16/3472
摘要： An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

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