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1. 发明申请

US20100172188A1 METHOD FOR CONDUCTING OVER-ERASE CORRECTION 有权
标题翻译：导致过度修正的方法
公开(公告)号：US20100172188A1
公开(公告)日：2010-07-08
申请号：US12350635
申请日：2009-01-08
申请人： CHUNG ZEN CHEN , CHUNG SHAN KUO , TZENG JU HSUE , CHING TSANN LEU
发明人： CHUNG ZEN CHEN , CHUNG SHAN KUO , TZENG JU HSUE , CHING TSANN LEU
IPC分类号： G11C16/06
CPC分类号： G11C16/3404 , G11C16/3409
摘要： A method for conducting an over-erase correction comprises the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a hot carrier HC soft program to correct over-erased cells if bit line leakage is found after the second erase and verification operation.
摘要翻译：进行过擦除校正的方法包括以下步骤：进行第一擦除和验证操作; 在第一擦除和验证操作之后，如果发现位线泄漏，则使用FN软程序校正过擦除的单元; 进行第二次擦除和验证操作; 并且如果在第二擦除和验证操作之后发现位线泄漏，则使用热载波HC软程序校正过擦除的单元。

2. 发明申请

US20110228623A1 POWER-UP CIRCUIT 有权
标题翻译：上电电路
公开(公告)号：US20110228623A1
公开(公告)日：2011-09-22
申请号：US12728508
申请日：2010-03-22
申请人： CHUNG ZEN CHEN
发明人： CHUNG ZEN CHEN
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/143
摘要： A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value. The second internal supply voltage potential detector is configured to detect a second internal supply voltage that is internal to the memory device and to receive the first detection signal and an output voltage of the first internal supply voltage potential detector for generating a third detection signal indicating whether the voltage potentials of the external supply voltage and the first and second internal supply voltages reach the first, second, and third predetermined values respectively. The logic circuit is configured to receive the third detection signal and to generate a power-up signal.
摘要翻译：上电电路包括外部电源电压检测器，第一内部电源电压检测器，第二内部电源电压电位检测器和逻辑电路。外部电源电压检测器被配置为检测存储器件外部的电源电压并产生指示外部电源电压的电压电位是否达到第一预定值的第一检测信号。第一内部电源电压检测器被配置为检测存储器件内部的第一内部电源电压并产生指示第一内部电源电压的电压电压是否达到第二预定值的第二检测信号。第二内部电源电压检测器被配置为检测存储器件内部的第二内部电源电压并且接收第一内部电源电压检测器的第一检测信号和第一内部电源电压检测器的输出电压，以产生指示是否外部电源电压和第一和第二内部电源电压的电压电位分别达到第一，第二和第三预定值。逻辑电路被配置为接收第三检测信号并产生上电信号。

3. 发明申请

US20110228627A1 DOUBLE DATA RATE MEMORY DEVICE HAVING DATA SELECTION CIRCUIT AND DATA PATHS 有权
标题翻译：具有数据选择电路和数据类型的双重数据速率存储器件
公开(公告)号：US20110228627A1
公开(公告)日：2011-09-22
申请号：US12728601
申请日：2010-03-22
申请人： CHUNG ZEN CHEN
发明人： CHUNG ZEN CHEN
IPC分类号： G11C8/16 , G11C7/06
CPC分类号： G11C7/1051 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1069 , G11C2207/107 , G11C2207/2272
摘要： A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.
摘要翻译：双数据速率存储器件包括第一和第二读出放大器，数据选择电路和数据处理电路。第一读出放大器被配置为提供加载在第一输入和输出数据线上的均匀数据，并且第二读出放大器被配置为提供加载在第二输入和输出数据线上的奇数数据。数据选择电路连接到第一和第二读出放大器，并且被配置为提供加载在单个数据线上的输出数据，以及数据处理电路，连接到数据选择电路并被配置为将偶数数据和奇数数据传送到第一和第二数据路径。偶数据和奇数据被组合到数据选择电路的输出数据中，并且数据选择电路响应于列地址的最低有效位选择输出数据，并将所选择的数据在单个数据线上传送响应时钟信号。

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