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1. 发明授权

US06197652B1 Fabrication method of a twin-tub capacitor 有权
标题翻译：双桶电容器的制造方法
公开(公告)号：US06197652B1
公开(公告)日：2001-03-06
申请号：US09326390
申请日：1999-06-04
申请人： Dahcheng Lin , Chih-Hsing Yu
发明人： Dahcheng Lin , Chih-Hsing Yu
IPC分类号： H01L218242
CPC分类号： H01L28/90 , H01L27/10852 , H01L28/84
摘要： A method of fabricating a twin-tub capacitor is described in which a dielectric layer is defined to form multiple column structures, followed by forming a conductive layer over the column structures. The conductive layer on the top surface of the column structures are removed by chemical mechanical polishing to isolate each capacitor. The column structures are further removed to form a twin-tub capacitor.
摘要翻译：描述了一种制造双层电容器的方法，其中限定介电层以形成多个列结构，然后在列结构上形成导电层。通过化学机械抛光除去柱结构的顶表面上的导电层以隔离每个电容器。进一步除去柱结构以形成双槽电容器。

2. 发明授权

US06624018B1 Method of fabricating a DRAM device featuring alternate fin type capacitor structures 有权
标题翻译：制造具有交替鳍式电容器结构的DRAM器件的方法
公开(公告)号：US06624018B1
公开(公告)日：2003-09-23
申请号：US09839965
申请日：2001-04-23
申请人： Chih-Hsing Yu , Chih-Yang Pai , Chia-Shiung Tsai
发明人： Chih-Hsing Yu , Chih-Yang Pai , Chia-Shiung Tsai
IPC分类号： H01L218242
CPC分类号： H01L28/87 , H01L27/0207 , H01L27/10817 , H01L27/10852
摘要： A process for fabricating an alternate fin type capacitor structure, used to increase capacitor surface area has been developed. The process features the formation of fin shaped, storage node structures, located in fin type capacitor openings, which are in turn defined in a group of composite insulator layers. A first fin type capacitor opening is formed by selectively creating lateral recesses in first type insulator layers, exposed in a first capacitor opening in the composite insulator layers, while an adjacent, second fin type capacitor opening is formed by selectively creating lateral recesses in second type insulator components, exposed in a second capacitor opening located in the same composite insulator layers. Portions of the lateral recesses in the first and second fin type capacitor openings overlay, allowing intertwined or alternate, storage node structures to be realized, thus reducing the space needed for the capacitor structure. The horizontal features of the fin shaped storage node structure, located in the lateral recesses, result in increased capacitor surface area when compared to counterparts fabricated without the lateral recess component.
摘要翻译：已经开发了用于制造用于增加电容器表面积的替代鳍式电容器结构的工艺。该方法的特征在于形成翅片形状的存储节点结构，其位于翅片式电容器开口中，其又限定在一组复合绝缘体层中。第一鳍型电容器开口通过选择性地产生在第一类型绝缘体层中形成的横向凹槽而形成，暴露在复合绝缘体层中的第一电容器开口中，而相邻的第二鳍状电容器开口通过选择性地产生第二类型的横向凹槽而形成绝缘体部件，暴露在位于同一复合绝缘体层中的第二电容器开口中。第一和第二鳍式电容器开口中的横向凹部的部分覆盖，允许实现相互缠绕或交替的存储节点结构，从而减少电容器结构所需的空间。与没有横向凹槽部件的制造商相比，位于横向凹槽中的翅片形储存结构的水平特征导致增加的电容器表面积。

3. 发明授权

US06531358B1 Method of fabricating capacitor-under-bit line (CUB) DRAM 有权
标题翻译：制造电容器下位线（CUB）DRAM的方法
公开(公告)号：US06531358B1
公开(公告)日：2003-03-11
申请号：US09850990
申请日：2001-05-09
申请人： Chih-Hsing Yu
发明人： Chih-Hsing Yu
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/10811 , H01L27/10888
摘要： A method for fabricating a CUB DRAM device having an enlarged process window for bit line contact patterning is deacribed. A plurality of capacitor node contact junctions and a bit line junction are provided in a semiconductor substrate. A node contact plug is formed through a first insulating layer to each of the capacitor node contact junctions. A bit line contact plug is formed to the bit line junction. Openings are etched through a second insulating layer to each of the node contact plugs. A polysilicon layer is conformally deposited within the openings and then recessed below the top of the openings wherein each of the polysilicon layers forms a bottom plate electrode of a capacitor. A capacitor dielectric layer is formed overlying the bottom plate electrodes and the second insulating layer. A polysilicon layer is deposited overlying the capacitor dialectic layer and patterned to form top capacitor plates overlying each of the bottom plate electrodes to complete the capacitors. An opening is etched through a third and the second insulating layers between the capacitors to the bit line contact plug and filled with a conducting layer to form a bit line to complete fabrication of a DRAM with CUB cell in an integrated circuit device.
摘要翻译：描述了一种用于制造具有放大的位线接触图案化处理窗口的CUB DRAM器件的方法。在半导体衬底中设置多个电容器节点接触结和位线结。节点接触插塞通过第一绝缘层形成到每个电容器节点接触接点。位线接触插塞形成到位线接点。开口通过第二绝缘层蚀刻到每个节点接触插塞。在开口内共形沉积多晶硅层，然后在开口顶部凹入，其中每个多晶硅层形成电容器的底板电极。在底板电极和第二绝缘层上形成电容器电介质层。沉积在电容器辩证层上的多晶硅层被图案化以形成覆盖每个底板电极的顶部电容器板，以完成电容器。将电容器之间的第三绝缘层和第二绝缘层蚀刻到位线接触插塞上，并填充导电层以形成位线，以在集成电路器件中完成具有CUB单元的DRAM的制造。

4. 发明授权

US06300191B1 Method of fabricating a capacitor under bit line structure for a dynamic random access memory device 有权
标题翻译：在动态随机存取存储器件的位线结构下制造电容器的方法
公开(公告)号：US06300191B1
公开(公告)日：2001-10-09
申请号：US09783382
申请日：2001-02-15
申请人： Chih-Hsing Yu , Kuo-Chi Tu
发明人： Chih-Hsing Yu , Kuo-Chi Tu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L21/76831 , H01L21/76877 , H01L21/76897 , H01L27/10811 , H01L27/10855
摘要： A process of forming a capacitor under bit line (CUB), structure, for a DRAM device, highlighted by simultaneous definition of the storage node structures, and a bit line contact structure, and by simultaneous definition of the capacitor top plate, and the bit line opening, has been developed. The process features forming a narrow diameter bit line contact hole, exposing a underlying polysilicon plug structure, while forming wider diameter, capacitor openings, to other underlying polysilicon plug structures. Polysilicon deposition, followed by a chemical mechanical polishing procedure, results in the simultaneous definition of the storage node, and bit line contact structures. Subsequent processing, comprising polysilicon and silicon oxide depositions, followed by an anisotropic RIE procedure, allow the definition of the capacitor structure to be defined simultaneously with the formation of a bit line opening.
摘要翻译：在存储节点结构的同时定义和位线接触结构突出显示的DRAM器件的位线（CUB）结构的结构，电容器顶板的同时定义以及位线开，已开发。该工艺特征在于形成窄直径位线接触孔，暴露下面的多晶硅插塞结构，同时形成更宽直径的电容器开口到其它下面的多晶硅插塞结构。多晶硅沉积，然后是化学机械抛光程序，导致存储节点和位线接触结构的同时定义。随后的包括多晶硅和氧化硅沉积的处理，随后是各向异性RIE程序，允许在形成位线开口的同时定义电容器结构。

5. 发明授权

US5819286A Video database indexing and query method and system 失效
标题翻译：视频数据库索引和查询方法和系统
公开(公告)号：US5819286A
公开(公告)日：1998-10-06
申请号：US570212
申请日：1995-12-11
申请人： Hsiao-Ying Yang , Cheng-Yao Ni , Chih-Hsing Yu , Chih-Chin Liu , Arbee L. P. Chen
发明人： Hsiao-Ying Yang , Cheng-Yao Ni , Chih-Hsing Yu , Chih-Chin Liu , Arbee L. P. Chen
IPC分类号： G06F17/30
CPC分类号： G06K9/00744 , G06F17/30831 , G06F17/30834 , G06K9/468 , Y10S707/99931 , Y10S707/99945
摘要： A video indexing and query execution system includes a processor which indexes video clips by: (a) identifying each symbol of one or more graphical icons in each frame of each video clip, (b) determining the horizontal, vertical and temporal coordinates of each symbol of the identified graphical icons, and (c) constructing a database for each identified symbol of the graphical icons. The processor converts a video query from graphical form to string form by: (a) receiving a video query specifying the vertical, horizontal and temporal coordinates of a graphical icon to be matched in at least one frame to be retrieved, and (b) constructing a normal 3-D string from the video query indicating the distance between each symbol of each icon in the video query in each direction. The processor also executes a video query on a video database by: (a) identifying only those video clips of the database whose signatures contain the signature of the executed video query, (b) for each of the identified video clips: (b1) constructing a 1-D list for each of the horizontal, vertical and temporal directions, comprising a plurality of sets of symbols of icons contained in video query, each set containing a permutation of symbols of the icons which satisfy the video query in the respective direction of the 1-D list, and (b2) forming the intersection of the three 1-D lists, and (c) identifying the portions of the video clips, indicated by a corresponding set contained in an intersection set of at least one of the identified video clips, as satisfying the video query.
摘要翻译：视频索引和查询执行系统包括：处理器，其通过以下步骤对视频剪辑进行索引：（a）识别每个视频剪辑的每个帧中的一个或多个图形图标的每个符号，（b）确定每个符号的水平，垂直和时间坐标的识别图形图标，以及（c）为图形图标的每个识别的符号构建数据库。处理器通过以下方式将视频查询转换成图形形式到字符串形式：（a）接收指定要在要检索的至少一个帧中匹配的图形图标的垂直，水平和时间坐标的视频查询，以及（b）构建来自视频查询的正常3-D字符串，指示每个方向上视频查询中每个图标的每个符号之间的距离。处理器还通过以下方式对视频数据库执行视频查询：（a）仅识别其签名包含执行的视频查询的签名的数据库的视频剪辑，（b）针对每个所识别的视频剪辑：（b1）构造用于水平，垂直和时间方向中的每一个的1-D列表，包括视频查询中包含的图标的多组符号集合，每个集合包含满足在相应方向上的视频查询的图标的符号排列所述1-D列表和（b2）形成三个1-D列表的交集，以及（c）识别由包含在所识别的至少一个的交集中的相应集合所指示的视频剪辑的部分视频剪辑，满足视频查询。

6. 发明授权

US06472266B1 Method to reduce bit line capacitance in cub drams 有权
标题翻译：减少崽子中位线电容的方法
公开(公告)号：US06472266B1
公开(公告)日：2002-10-29
申请号：US09882427
申请日：2001-06-18
申请人： Chih-Hsing Yu , Yu-Shen Chen
发明人： Chih-Hsing Yu , Yu-Shen Chen
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L21/7682 , H01L27/10811 , H01L28/84 , H01L28/90
摘要： A new method is provided for the creation of the bit line contact plug. CUB capacitors typically are located adjacent to the bit line contact plug, a parasitic capacitance therefore exists between the CUB and the contact plug. Typical interface between the CUB and the bit line contact plug consists of a dielectric. By creating an air gap that partially replaces the dielectric between the CUB and the bit line contact plug, the dielectric constant of the interface between the bit line and the CUB is reduced, thereby reducing the parasitic coupling between the bit line contact plug and the CUB. This enables the creation of CUB capacitors of increased height, making the CUB and the therewith created DRAM devices better suited for the era of sub-micron device dimensions.
摘要翻译：提供了一种用于创建位线接触插头的新方法。 CUB电容器通常位于与位线接触插塞相邻的位置，因此在CUB和接触插头之间存在寄生电容。 CUB和位线接触插头之间的典型接口由电介质组成。通过产生部分地替代CUB和位线接触插塞之间的电介质的气隙，位线和CUB之间的界面的介电常数减小，从而减小位线接触插塞和CUB之间的寄生耦合。这使得能够创建增加高度的CUB电容器，使得CUB和由此产生的DRAM器件更适合于亚微米器件尺寸的时代。

7. 发明授权

US07033846B2 Method for manufacturing semiconductor devices by monitoring nitrogen bearing species in gate oxide layer 有权
标题翻译：通过监测栅氧化层中的氮含量来制造半导体器件的方法
公开(公告)号：US07033846B2
公开(公告)日：2006-04-25
申请号：US10796614
申请日：2004-03-08
申请人： Chih-Hsing Yu
发明人： Chih-Hsing Yu
IPC分类号： G01R31/26 , H01L21/31
CPC分类号： H01L21/28202 , H01L21/28185 , H01L21/3144 , H01L22/20 , H01L22/34 , H01L29/513 , H01L29/518
摘要： A method for processing integrated circuit devices. The method includes introducing a test wafer into a production run of wafers to form a run of wafers to be processed. Each of the wafers is before a gate dielectric production process. The method inserts the run of wafers into a process for gate dielectric production, e.g., gate oxide. The method forms a silicon oxynitride layer to a predetermined thickness of less than 30 Angstroms at a predetermined temperature using a nitrogen bearing species and an oxygen bearing species, alone or in combination. The method removes the test wafer from the run and forms a second oxidation overlying the silicon oxynitride layer to a second thickness, which is based substantially upon a nitrogen bearing concentration in the silicon oxynitride layer. The method determines a difference value between the first predetermined thickness and the second thickness. A step of correlating the difference value to one of a plurality of nitrogen concentrations to determine a nitrogen concentration in the first predetermined thickness is included.
摘要翻译：一种用于处理集成电路器件的方法。该方法包括将测试晶片引入到晶片的生产运行中以形成待处理晶片的行程。每个晶片在栅极电介质制造工艺之前。该方法将晶片的行程插入用于栅极电介质生产的工艺中，例如栅极氧化物。该方法单独或组合地使用含氮物种和含氧物种在预定温度下形成预定厚度小于30埃的氧氮化硅层。该方法从运行中移除测试晶片，并且形成覆盖氮氧化硅层的第二氧化膜至基本上基于氮氧化硅层中含氮浓度的第二厚度。该方法确定第一预定厚度和第二厚度之间的差值。包括将差值与多个氮浓度中的一个相关联以确定第一预定厚度中的氮浓度的步骤。

8. 发明授权

US06555442B1 Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer 有权
标题翻译：通过使用一次性间隔件形成具有圆角和无凹槽的浅沟槽隔离的方法
公开(公告)号：US06555442B1
公开(公告)日：2003-04-29
申请号：US10042075
申请日：2002-01-08
申请人： Chih-Yang Pai , Chih-Hsing Yu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
发明人： Chih-Yang Pai , Chih-Hsing Yu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of fabricating an STI, comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers. An STI oxide layer is formed over the patterned hard mask layer, filling the liner oxide layer lined STI opening. The STI oxide layer is planarized and the patterned hard mask, the patterned undoped poly buffer layer and the patterned pad oxide layer are removed to fabricate the STI having rounded corners and without substantial divots.
摘要翻译：一种制造STI的方法，包括以下步骤。提供了具有形成在其上的衬垫氧化物层的硅结构。在衬垫氧化物层上形成未掺杂的多晶缓冲层。在未掺杂的多缓冲层上形成硬掩模层。将硬掩模层，未掺杂的多晶缓冲层和焊盘氧化物层图案化以形成暴露有源区域内的硅结构的一部分的开口。开口具有暴露的侧壁。在暴露的侧壁上形成无机间隔物。使用图案化的硬掩模层和间隔物作为硬掩模，蚀刻硅结构以在有效区域内形成STI开口。去除暴露STI开口的上角的无机间隔物。使用氧化工艺，在STI开口内，在STI开口的上角上形成衬里氧化物层，并且至少通过去除无机间隔物露出图案化的未掺杂多缓冲层。在图案化的硬掩模层之上形成STI氧化物层，填充衬里氧化物层衬里的STI开口。将STI氧化物层平坦化，并且去除图案化的硬掩模，图案化的未掺杂多缓冲层和图案化的衬垫氧化物层，以制造具有圆角并且没有实质上的纹理的STI。

9. 发明授权

US06294426B1 Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole 有权
标题翻译：在增加电容的位线结构下制造电容器的方法，而不增加干蚀刻位线接触孔的纵横比
公开(公告)号：US06294426B1
公开(公告)日：2001-09-25
申请号：US09765041
申请日：2001-01-19
申请人： Kuo-Chi Tu , Chih-Hsing Yu
发明人： Kuo-Chi Tu , Chih-Hsing Yu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L27/10855 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： A process for fabricating a capacitor under bit line (CUM), DRAM device, featuring increased capacitance, without increasing the aspect ratio for a dry etched, narrow diameter bit line contact hole, has been developed. The process features increasing the vertical space in a capacitor opening, needed to accommodate a capacitor structure with increased vertical dimensions, via selective removal of the top portions of the polysilicon plug structures exposed in the capacitor openings. The depth of a subsequent bit line contact hole, opened to a non-truncated polysilicon plug structure, is therefore not increased as a result of the increase capacitor depth, thus not resulting in an increased aspect ratio for the dry etched, narrow diameter bit line contact hole.
摘要翻译：已经开发了用于在位线（CUM）下制造电容器的过程，具有增加的电容的DRAM器件，而不增加用于干蚀刻的窄直径位线接触孔的纵横比。该方法特征在于，通过选择性地去除暴露在电容器开口中的多晶硅插塞结构的顶部部分，增加电容器开口中垂直空间，以容纳具有增加的垂直尺寸的电容器结构。因此，由于增加了电容器的深度，所以随后的位线接触孔的深度开放到非截短多晶硅插塞结构，因此不会增加干蚀刻的窄直径位线的纵横比接触孔。

10. 发明授权

US6100136A Method of fabricating capacitor capable of maintaining the height of the peripheral area of the capacitor 有权
标题翻译：制造能够保持电容器外围区域高度的电容器的方法
公开(公告)号：US6100136A
公开(公告)日：2000-08-08
申请号：US342718
申请日：1999-06-29
申请人： Dahcheng Lin , Chih-Hsing Yu
发明人： Dahcheng Lin , Chih-Hsing Yu
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10894 , H01L28/91 , H01L27/10852
摘要： A method of forming a capacitor. A substrate comprises a cell array area and a peripheral area. A dielectric layer is formed on the substrate. The covering layer is formed on the dielectric layer. The contact electrode is formed through the dielectric layer and the covering layer. The first oxide layer is formed over the substrate. A portion of the first oxide layer is removed to form an opening, which exposes the contact electrode. A conformal preserve layer is formed over the substrate. A second oxide layer is formed over the substrate. A portion of the second oxide layer in the cell array area is removed to form an opening, which exposes the contact electrode. A conformal first conductive layer is formed over the substrate to cover the second oxide layer and the opening. A third oxide layer is formed over the substrate to cover the first conductive layer and fill the opening. A planarization step is performed to remove the third oxide layer, the first conductive layer, and the second oxide layer until the preserve layer in the peripheral area is exposed. The third oxide layer and the second oxide layer in the cell array area are removed to expose conductive layer. A selective hemispherical grained silicon layer and a dielectric film are formed in sequence over the exposed conductive layer. A second conductive layer is formed over the substrate to fill the opening.
摘要翻译：一种形成电容器的方法。基板包括单元阵列区域和外围区域。在基板上形成电介质层。覆盖层形成在电介质层上。接触电极通过电介质层和覆盖层形成。第一氧化物层形成在衬底上。去除第一氧化物层的一部分以形成露出接触电极的开口。在衬底上形成保形层。在衬底上形成第二氧化物层。去除单元阵列区域中的第二氧化物层的一部分以形成露出接触电极的开口。在衬底上形成共形的第一导电层以覆盖第二氧化物层和开口。第三氧化物层形成在衬底上以覆盖第一导电层并填充开口。执行平面化步骤以去除第三氧化物层，第一导电层和第二氧化物层，直到外围区域中的保护层被暴露。去除单元阵列区域中的第三氧化物层和第二氧化物层以暴露导电层。在暴露的导电层上依次形成选择性半球形硅层和电介质膜。第二导电层形成在衬底上以填充开口。

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