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1. 发明申请

US20130016135A1 DISPLAY SYSTEM AND CONTROL METHOD THEREOF 审中-公开
标题翻译：显示系统及其控制方法
公开(公告)号：US20130016135A1
公开(公告)日：2013-01-17
申请号：US13542613
申请日：2012-07-05
申请人： Shou-Cheng WANG , Tse-Yuan CHEN , Chih-Chiang TSENG , Du-Zen PENG
发明人： Shou-Cheng WANG , Tse-Yuan CHEN , Chih-Chiang TSENG , Du-Zen PENG
IPC分类号： G09G5/10
CPC分类号： G09G3/3233 , G09G2300/0452 , G09G2300/0819 , G09G2300/0861 , G09G2320/043 , G09G2320/103 , G09G2330/021 , G09G2340/0435
摘要： A display system including a driving circuit and a display panel is disclosed. The display panel displays an image according to the data signals and the scan signals and includes a first driving unit, a second driving unit, a first luminous element, a second luminous element and a third luminous element. The first driving unit includes a first driving transistor to generate a first driving current. The second driving unit includes a second driving transistor to generate a second driving current. The first luminous element is lighted according to the first driving current when a first emitting signal is activated. The second luminous element is lighted according to the first driving current when a second emitting signal is activated. The third luminous element is lighted according to the second driving current when the first emitting signal is activated.
摘要翻译：公开了一种包括驱动电路和显示面板的显示系统。显示面板根据数据信号和扫描信号显示图像，并且包括第一驱动单元，第二驱动单元，第一发光元件，第二发光元件和第三发光元件。第一驱动单元包括产生第一驱动电流的第一驱动晶体管。第二驱动单元包括产生第二驱动电流的第二驱动晶体管。当第一发光信号被激活时，第一发光元件根据第一驱动电流点亮。当第二发光信号被激活时，第二发光元件根据第一驱动电流点亮。当第一发光信号被激活时，第三发光元件根据第二驱动电流点亮。

2. 发明授权

US07646215B2 Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus 有权
标题翻译：在双向数据总线上实现可编程阻抗输出驱动器和芯片端接上的可编程输入的高效方法
公开(公告)号：US07646215B2
公开(公告)日：2010-01-12
申请号：US12079100
申请日：2008-03-24
申请人： Robert B. Haig , Patrick T. Chuang , Chih-Chiang Tseng , Kookhwan Kwon
发明人： Robert B. Haig , Patrick T. Chuang , Chih-Chiang Tseng , Kookhwan Kwon
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H04L25/0278
摘要： A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver mode or a termination mode while maintaining minimum associated capacitance.
摘要翻译：组合的输入和终端电路包括阻抗的固定部分和阻抗的可编程部分。固定部分能够以驾驶员模式和终止模式被固定。可编程部分能够被配置为具有在驱动器模式或终止模式下的期望阻抗，同时保持最小相关电容。

3. 发明授权

US07516385B2 Test semiconductor device in full frequency with half frequency tester 有权
标题翻译：半频测试仪全速测试半导体器件
公开(公告)号：US07516385B2
公开(公告)日：2009-04-07
申请号：US11414612
申请日：2006-04-28
申请人： Chih-Chiang Tseng , Hsin-Ley Suzanne Chen , Jae-Hyeong Kim
发明人： Chih-Chiang Tseng , Hsin-Ley Suzanne Chen , Jae-Hyeong Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/31922
摘要： An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock and test data signals at a normal (1× mode) and high-speed rate (2× mode) to a device under test. In 1× mode, clock generator and test data generator circuits pass through the differential clock signals and test data values provided by a testing device unchanged. In 2× mode, the clock generator circuit receives the differential clock signal as clock signals clk and clkb and outputs clock signals clk_int and clkb_int that are inverted signals and twice the frequency of clk and clkb. The test data generator circuit clocks test data values into registers according to clk_int and clkb_int to generate an increased number of test data values per clock signal clk.
摘要翻译：集成电路包括双频时钟发生器和双输入发生器，以使用半频测试仪来测试半频率器件的边缘频率。时钟发生器电路和测试数据发生器电路以正常（1x模式）和高速率（2x模式）向待测器件提供差分时钟和测试数据信号。在1x模式下，时钟发生器和测试数据发生器电路通过差分时钟信号和测试设备提供的测试数据值不变。在2x模式下，时钟发生器电路接收作为时钟信号clk和clkb的差分时钟信号，并输出作为反相信号的时钟信号clk_int和clkb_int，是clk和clkb的两倍频率。测试数据发生器电路根据clk_int和clkb_int将测试数据值转换为寄存器，以产生每个时钟信号clk增加的测试数据值。

4. 发明授权

US07400157B2 Composite wiring structure having a wiring block and an insulating layer with electrical connections to probes 失效
标题翻译：复合布线结构具有布线块和与探针电连接的绝缘层
公开(公告)号：US07400157B2
公开(公告)日：2008-07-15
申请号：US11692035
申请日：2007-03-27
申请人： Gary W. Grube , Igor Y. Khandros , Benjamin N. Eldridge , Gaetan L. Mathieu , Poya Lotfizadeh , Chih-Chiang Tseng
发明人： Gary W. Grube , Igor Y. Khandros , Benjamin N. Eldridge , Gaetan L. Mathieu , Poya Lotfizadeh , Chih-Chiang Tseng
IPC分类号： G01R31/02 , G06F17/50 , H01L29/10 , H05K3/36
CPC分类号： G01R31/2886 , G01R1/07314 , G01R1/07342 , G01R1/07357 , G01R1/07378 , G01R3/00 , Y10T29/49126
摘要： A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.
摘要翻译：一种设计和制造探针卡组件的方法包括将探针卡组件的一个或多个元件预制成一个或多个预定的设计。此后，接收关于新设计的半导体器件的设计数据以及描述用于测试半导体器件的测试器和测试算法的数据。使用接收到的数据，选择一个或多个预制元素。再次使用接收的数据，定制一个或多个所选择的预制元素。然后使用选定和定制的元件构建探针卡组件。

5. 发明申请

US20070266286A1 Test semiconductor device in full frequency with half frequency tester 有权
标题翻译：半频测试仪全速测试半导体器件
公开(公告)号：US20070266286A1
公开(公告)日：2007-11-15
申请号：US11414612
申请日：2006-04-28
申请人： Chih-Chiang Tseng , Hsin-Ley Chen , Jae-Hyeong Kim
发明人： Chih-Chiang Tseng , Hsin-Ley Chen , Jae-Hyeong Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/31922
摘要： An integrated circuit includes a double frequency clock generator and a double input generator to test semiconductor devices at full frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock signals and test data signals at a normal rate (1× mode) and a high speed rate (2× mode) to a device under test. In the 1× mode, the clock generator circuit and the test data generator circuit pass through the differential clock signals and test data values provided by a testing device unchanged. In the 2× mode, the clock generator circuit receives the differential clock signal as a clock signal clk and a clock signal clkb 90 degrees out of phase, and outputs a clock signal clk_int and a clock signal clkb_int that are inverted signals of each other and that are twice the frequency of the clock signal clk and the clock signal clkb. In the 2× mode, the test data generator circuit receives the test data values from the testing device and clocks the test data values into registers according to the clock signal clk_int and the clock signal clkb_int in order to generate an increased number of test data values per the clock signal clk.
摘要翻译：集成电路包括双频时钟发生器和双输入发生器，以使用半频测试仪在全频率下测试半导体器件。时钟发生器电路和测试数据发生器电路以正常速率（1x模式）和高速率（2x模式）向待测器件提供差分时钟信号和测试数据信号。在1x模式下，时钟发生器电路和测试数据发生器电路通过差分时钟信号和测试设备提供的测试数据值不变。在2x模式下，时钟发生器电路将差分时钟信号作为时钟信号clk和相位90度的时钟信号clk接收，并且输出作为彼此反相信号的时钟信号clk_int和时钟信号clkb_int，时钟信号clk_int和时钟信号clkb_int是彼此的反相信号，是时钟信号clk和时钟信号clkb的两倍频率。在2x模式下，测试数据发生器电路从测试装置接收测试数据值，并根据时钟信号clk_int和时钟信号clkb_int将测试数据值计时到寄存器中，以产生每个测试数据值增加的数量时钟信号clk。

6. 发明申请

US20070247176A1 Method of Manufacturing a Probe Card 失效
标题翻译：制造探针卡的方法
公开(公告)号：US20070247176A1
公开(公告)日：2007-10-25
申请号：US11692035
申请日：2007-03-27
申请人： Gary Grube , Igor Khandros , Benjamin Eldridge , Gaetan Mathieu , Poya Lotfizadeh , Chih-Chiang Tseng
发明人： Gary Grube , Igor Khandros , Benjamin Eldridge , Gaetan Mathieu , Poya Lotfizadeh , Chih-Chiang Tseng
IPC分类号： G01R31/26 , G01R31/04
CPC分类号： G01R31/2886 , G01R1/07314 , G01R1/07342 , G01R1/07357 , G01R1/07378 , G01R3/00 , Y10T29/49126
摘要： A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.
摘要翻译：一种设计和制造探针卡组件的方法包括将探针卡组件的一个或多个元件预制成一个或多个预定的设计。此后，接收关于新设计的半导体器件的设计数据以及描述用于测试半导体器件的测试器和测试算法的数据。使用接收到的数据，选择一个或多个预制元素。再次使用接收的数据，定制一个或多个所选择的预制元素。然后使用选定和定制的元件构建探针卡组件。

7. 发明申请

US20070080697A1 Semiconductor device tester pin contact resistance measurement 审中-公开
标题翻译：半导体器件测试器引脚接触电阻测量
公开(公告)号：US20070080697A1
公开(公告)日：2007-04-12
申请号：US11413219
申请日：2006-04-28
申请人： Chih-Chiang Tseng , Patrick Chuang , Chungji Lu
发明人： Chih-Chiang Tseng , Patrick Chuang , Chungji Lu
IPC分类号： G01R27/08
CPC分类号： G01R27/205 , G01R31/2886
摘要： A contact resistance measuring circuit is configured to determine the contact resistance of a testing device. The measuring circuit is coupled to a processing circuit and the testing device. The measuring circuit includes a pair of input/output units coupled together via a pass device. Each of the input/output units includes a pull-up device and a pull-down device to provide separate pull-up and pull-down control, respectively. The pull-up devices, the pull-down devices, and the pass device are dynamically configurable such that the measuring circuit uses either a pull-up mode or a pull-down mode to measure voltage and current characteristics of each contact point, or pin, of the testing device. The processing circuit calculates the contact resistance for each pin according to the measured voltage and current characteristics. The calculated contact resistances are used to calibrate the testing device.
摘要翻译：接触电阻测量电路被配置为确定测试装置的接触电阻。测量电路耦合到处理电路和测试装置。测量电路包括经由通过装置耦合在一起的一对输入/输出单元。每个输入/输出单元包括分别上拉和下拉控制的上拉装置和下拉装置。上拉器件，下拉器件和通过器件是可动态配置的，使得测量电路使用上拉模式或下拉模式来测量每个触点或引脚的电压和电流特性，测试设备。处理电路根据测量的电压和电流特性来计算每个引脚的接触电阻。计算的接触电阻用于校准测试装置。

8. 发明授权

US06864105B2 Method of manufacturing a probe card 失效
标题翻译：探针卡的制造方法
公开(公告)号：US06864105B2
公开(公告)日：2005-03-08
申请号：US10087081
申请日：2002-03-01
申请人： Gary W. Grube , Igor Y. Khandros , Benjamin N. Eldridge , Gaetan L. Mathieu , Poya Lotfizadeh , Chih-Chiang Tseng
发明人： Gary W. Grube , Igor Y. Khandros , Benjamin N. Eldridge , Gaetan L. Mathieu , Poya Lotfizadeh , Chih-Chiang Tseng
IPC分类号： G01R31/26 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R1/07314 , G01R1/07342 , G01R1/07378 , G01R3/00 , G01R31/2886 , G01R31/2889 , Y10T29/49002 , Y10T29/49004 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49453
摘要： A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.
摘要翻译：一种设计和制造探针卡组件的方法包括将探针卡组件的一个或多个元件预制成一个或多个预定的设计。此后，接收关于新设计的半导体器件的设计数据以及描述用于测试半导体器件的测试器和测试算法的数据。使用接收到的数据，选择一个或多个预制元素。再次使用接收的数据，定制一个或多个所选择的预制元素。然后使用选定和定制的元件构建探针卡组件。

9. 发明申请

US20090212790A1 METHOD OF ESTIMATING CHANNEL BANDWIDTH FROM A TIME DOMAIN REFLECTOMETER (TDR) MEASUREMENT 审中-公开
标题翻译：估计来自时域反射计（TDR）测量的通道带宽的方法
公开(公告)号：US20090212790A1
公开(公告)日：2009-08-27
申请号：US12431037
申请日：2009-04-28
申请人： Charles A. Miller , Jim Chih-Chiang Tseng
发明人： Charles A. Miller , Jim Chih-Chiang Tseng
IPC分类号： G01R27/06
CPC分类号： G01R27/04
摘要： Bandwidth of a test channel is determined from a single port Time Domain Reflectometer (TDR) measurement with the channel terminated in a short or an open circuit. Bandwidth is estimated by: (1) making a TDR measurement of a channel terminated in a short or open circuit; (2) determining a maximum slope of the reflection from the TDR measurement; (2) calculating an interpolated rise or fall time, for example by taking 80% of the applied voltage between the 10% and 90% points, and then dividing the applied voltage by the maximum slope determined; (3) dividing the overall interpolated rise time by the square root of two to account for the TDR signal proceeding through the channel twice; (4) removing the contribution of rise time from measurement equipment; and (5) completing calculation of channel bandwidth using a formula to relate bandwidth to rise time, such as: bandwidth=0.35/rise time.
摘要翻译：测试通道的带宽由单端口时域反射计（TDR）测量确定，通道以短路或开路端接。带宽通过以下方式估计：（1）使TDR测量在短路或开路中终止; （2）从TDR测量确定反射的最大斜率; （2）例如通过将所施加的电压的80％乘以10％和90％之间的点来计算内插的上升或下降时间，然后将所施加的电压除以所确定的最大斜率; （3）将整体内插上升时间除以二的平方根以考虑通过信道进行的TDR信号两次; （4）消除测量设备上升时间的贡献; 并且（5）使用公式来完成信道带宽的计算，以将带宽与上升时间相关联，例如：带宽= 0.35 /上升时间。

10. 发明授权

US07525302B2 Method of estimating channel bandwidth from a time domain reflectometer (TDR) measurement using rise time and maximum slope 失效
标题翻译：使用上升时间和最大斜率从时域反射计（TDR）测量中估计通道带宽的方法
公开(公告)号：US07525302B2
公开(公告)日：2009-04-28
申请号：US11048383
申请日：2005-01-31
申请人： Charles A. Miller , Jim Chih-Chiang Tseng
发明人： Charles A. Miller , Jim Chih-Chiang Tseng
IPC分类号： G01R27/04
CPC分类号： G01R27/04
摘要： Bandwidth of a test channel is determined from a single port Time Domain Reflectometer (TDR) measurement with the channel terminated in a short or an open circuit. Bandwidth is estimated by: (1) making a TDR measurement of a channel terminated in a short or open circuit; (2) determining a maximum slope of the reflection from the TDR measurement; (3) calculating an interpolated rise or fall time, for example by taking 80% of the applied voltage between the 10% and 90% points, and then dividing the applied voltage by the maximum slope determined; (4) dividing the overall interpolated rise time by the square root of two to account for the TDR signal proceeding through the channel twice; (5) removing the contribution of rise time from measurement equipment; and (6) completing calculation of channel bandwidth using a formula to relate bandwidth to rise time, such as: bandwidth=0.35/rise time.
摘要翻译：测试通道的带宽由单端口时域反射计（TDR）测量确定，通道以短路或开路端接。带宽通过以下方式估计：（1）使TDR测量在短路或开路中终止; （2）从TDR测量确定反射的最大斜率; （3）例如通过将所施加的电压的80％乘以10％至90％的点来计算内插的上升或下降时间，然后将所施加的电压除以所确定的最大斜率; （4）将整体内插上升时间除以二的平方根以考虑通过通道进行的TDR信号两次; （5）消除测量设备上升时间的贡献; 和（6）使用公式来完成信道带宽的计算，以将带宽与上升时间相关联，例如：带宽= 0.35 /上升时间。

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