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1. 发明授权

US06771654B1 Apparatus and method for sharing memory using a single ring data bus connection configuration 失效
标题翻译：使用单环数据总线连接配置共享存储器的装置和方法
公开(公告)号：US06771654B1
公开(公告)日：2004-08-03
申请号：US09562924
申请日：2000-05-02
申请人： Jinqlih (Charlie) Sang , Shashank Merchant
发明人： Jinqlih (Charlie) Sang , Shashank Merchant
IPC分类号： H04L1254
CPC分类号： H04L12/42
摘要： Multiple network switches are configured having memory interfaces that transfer segmented packet data to each other via a unidirectional data bus ring connecting the network switches in a single ring or “daisy chain” arrangement. The memory interfaces are also configured for transferring the segmented packet data to respective local buffer memories for temporary storage. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by requiring only one read and one write operation to and from the local buffer memory for each segmented packet data being received and transmitted through the switches.
摘要翻译：多个网络交换机被配置为具有通过以单环或“菊花链”布置连接网络交换机的单向数据总线环来将分段分组数据彼此传送的存储器接口。存储器接口还被配置为将分段分组数据传送到相应的本地缓冲存储器用于临时存储。存储器接口根据规定的顺序传送数据单元，通过对通过交换机接收和发送的每个分段分组数据仅需要对本地缓冲存储器进行一次读取和一次写入操作来优化存储器带宽。

2. 发明授权

US1426677A Transmission mechanism 失效
公开(公告)号：US1426677A
公开(公告)日：1922-08-22
申请号：US36667720
申请日：1920-03-17
申请人： CHARLIE SANG
发明人： CHARLIE SANG
IPC分类号： F16H3/16
CPC分类号： F16H3/16 , Y10T74/19242

3. 发明授权

US06891843B1 Apparatus and method for sharing memory using extra data path having multiple rings 失效
标题翻译：用于使用具有多个环的附加数据路径共享存储器的装置和方法
公开(公告)号：US06891843B1
公开(公告)日：2005-05-10
申请号：US09562927
申请日：2000-05-02
申请人： Jinqlih (Charlie) Sang , Shashank Merchant
发明人： Jinqlih (Charlie) Sang , Shashank Merchant
IPC分类号： H04L12/427 , H04L12/56 , H04L12/28 , H04J3/24
CPC分类号： H04L49/15 , H04L12/427 , H04L49/102 , H04L49/103 , H04L49/3018 , H04L49/3072 , H04L49/351 , H04L49/45
摘要： Multiple network switches are configured having memory interfaces that transfer segmented frame data to each other via a data path having multiple rings connecting the network switches. The memory interfaces are also configured for transferring the segmented frame data to respective local buffer memories for temporary storage. The data path transfers the data units between the switches according to a prescribed sequence protocol, optimizing memory bandwidth by requiring only one read and one write operation to and from a local buffer memory for each segmented frame data being received and transmitted through the switches.
摘要翻译：多个网络交换机被配置成具有通过具有连接网络交换机的多个环的数据路径将分段帧数据彼此传送的存储器接口。存储器接口还被配置为将分段的帧数据传送到相应的本地缓冲存储器用于临时存储。数据路径根据规定的顺序协议在交换机之间传输数据单元，通过仅通过交换机接收和发送的每个分段帧数据仅需要对本地缓冲存储器进行一次读取和一次写入操作来优化存储器带宽。

4. 发明授权

US06741589B1 Apparatus and method for storing data segments in a multiple network switch system using a memory pool 有权
标题翻译：用于使用存储器池将数据段存储在多个网络交换机系统中的装置和方法
公开(公告)号：US06741589B1
公开(公告)日：2004-05-25
申请号：US09562003
申请日：2000-05-02
申请人： Jinqlih (Charlie) Sang , Shashank Merchant
发明人： Jinqlih (Charlie) Sang , Shashank Merchant
IPC分类号： H04L1256
CPC分类号： H04L49/103 , H04L49/102 , H04L49/351 , H04L49/90
摘要： Multiple network switch modules have memory interfaces configured for transferring packet data to respective local buffer memories via local memory controllers. The local memory controllers are connected to each other to form a signal memory pool for transfer among each other data units of data frames received from different network switch modules. Each of the controllers are also connected to a corresponding local buffer memory and either write received data units in the corresponding local buffer memory or transfer the received data units to other controllers that, in turn, write the data units in their corresponding local buffer memory. The local memory controllers transfer and write and read the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads.
摘要翻译：多个网络交换机模块具有配置用于经由本地存储器控制器将分组数据传送到相应的本地缓冲存储器的存储器接口。本地存储器控制器彼此连接以形成信号存储池，用于在从不同网络交换机模块接收的数据帧的彼此之间传送数据单元。每个控制器还连接到相应的本地缓冲存储器，并且将相应的本地缓冲存储器中的接收数据单元写入或将接收到的数据单元传送到其他控制器，而控制器又将数据单元写入其对应的本地缓冲存储器。本地存储器控制器根据规定的顺序传送和读取和读取数据单元，通过同时执行规定数量的连续存储器写入或存储器读取来优化存储器带宽。

5. 发明授权

US06463478B1 Method and apparatus for identifying runt data frames received by a network switch 有权
标题翻译：用于识别由网络交换机接收的寻线数据帧的方法和装置
公开(公告)号：US06463478B1
公开(公告)日：2002-10-08
申请号：US09316179
申请日：1999-05-21
申请人： Michael Vengchong Lau , Charlie Sang
发明人： Michael Vengchong Lau , Charlie Sang
IPC分类号： G06F1128
CPC分类号： H04L29/06 , H04L43/00 , H04L43/16 , H04L47/30 , H04L49/205 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L69/324
摘要： An apparatus and method for detecting runt data frames received by a network switch includes a plurality of queuing logics, corresponding to the number of ports contained in the network switch. The queuing logics transfer received data frames to a memory area of the network switch. The queuing logics also update the value of a column write pointer that indicates the number of data transfers required to store a prescribed portion of a particular received data frame in the memory area. A rules queue examines the column write pointer and determines if the particular data frame is a runt data frame. A runt indication signal is generated, after the particular data frame has been completely transferred to the memory area, in order to indicate if the particular data frame was a runt data frame.
摘要翻译：一种用于检测由网络交换机接收的无线数据帧的装置和方法，包括与网络交换机中包含的端口数相对应的多个排队逻辑。排队逻辑传输将数据帧接收到网络交换机的存储区域。排队逻辑还更新列写入指针的值，其指示将特定接收数据帧的规定部分存储在存储器区域中所需的数据传送的数量。规则队列检查列写入指针，并确定特定数据帧是否是欠锁数据帧。在特定数据帧已经被完全传送到存储器区域之后，产生欠压指示信号，以便指示特定数据帧是否是欠幅数据帧。

6. 发明授权

US1580683A Potato cleaning and sacking machine 失效
标题翻译：马铃薯清洗和解袋机
公开(公告)号：US1580683A
公开(公告)日：1926-04-13
申请号：US36667820
申请日：1920-03-17
申请人： CHARLIE SANG
发明人： CHARLIE SANG
IPC分类号： A01D17/10
CPC分类号： A01D17/10 , A01D2017/103

7. 发明授权

US5845139A System for providing a host computer with access to a memory on a PCMCIA card in a power down mode 失效
标题翻译：用于提供主机在断电模式下访问PCMCIA卡上的存储器的系统
公开(公告)号：US5845139A
公开(公告)日：1998-12-01
申请号：US487316
申请日：1995-06-07
申请人： Matthew J. Fischer , Charlie Sang
发明人： Matthew J. Fischer , Charlie Sang
IPC分类号： G06F1/26 , G06F1/04 , G06F1/32 , G06K17/00 , G06K19/07
CPC分类号： G06F1/3215
摘要： A wake-up system is provided to allow host computer access to a Card Information Structure (CIS) on a PCMCIA card during a SLEEP mode. The CIS is stored in a non-volatile memory accessible to a host computer via a PCMCIA bus and to PCMCIA card logic via a local bus. Arbitration logic is coupled between the PCMCIA and local buses to control access to the memory. Sleep logic prevents a fast clock signal from being supplied to the arbitration logic and the PCMCIA card logic when the PCMCIA card is switched into the SLEEP mode. A CIS read detect circuit decodes a CIS read operation on the PCMCIA bus and asserts the CIS detect signal supplied to the sleep logic. In response, the sleep logic allows the fast clock signals to be supplied to the arbitration logic and adapter card subsystem to exit from the SLEEP mode and provide the host computer with access to the memory storing the CIS information.
摘要翻译：提供唤醒系统，以允许主机在休眠模式下访问PCMCIA卡上的卡信息结构（CIS）。 CIS存储在主机通过PCMCIA总线可访问的非易失性存储器中，并通过本地总线存储到PCMCIA卡逻辑。仲裁逻辑耦合在PCMCIA和本地总线之间，以控制对存储器的访问。当PCMCIA卡切换到休眠模式时，休眠逻辑可防止将快速时钟信号提供给仲裁逻辑和PCMCIA卡逻辑。 CIS读取检测电路解码PCMCIA总线上的CIS读取操作，并断言提供给睡眠逻辑的CIS检测信号。作为响应，睡眠逻辑允许将快速时钟信号提供给仲裁逻辑和适配器卡子系统以退出休眠模式，并向主机提供对存储CIS信息的存储器的访问。

8. 发明授权

US1480351A Ratchet mechanism for agricultural implements 失效
标题翻译：农具棘轮机构
公开(公告)号：US1480351A
公开(公告)日：1924-01-08
申请号：US38933420
申请日：1920-06-16
申请人： CHARLIE SANG
发明人： CHARLIE SANG
IPC分类号： A01B71/00
CPC分类号： A01B71/00

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