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1. 发明申请

US20130334593A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20130334593A1
公开(公告)日：2013-12-19
申请号：US13972533
申请日：2013-08-21
申请人： Kwang-Soo SEOL , Chanjin PARK , Ki-Hyun HWANG , Hanmei CHOI , Sunghoi HUR , Wansik HWANG , Toshiro NAKANISHI , Kwangmin PARK , Ju-Yul LEE
发明人： Kwang-Soo SEOL , Chanjin PARK , Ki-Hyun HWANG , Hanmei CHOI , Sunghoi HUR , Wansik HWANG , Toshiro NAKANISHI , Kwangmin PARK , Ju-Yul LEE
IPC分类号： H01L29/792
CPC分类号： H01L29/42348 , H01L21/32137 , H01L27/0688 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/511 , H01L29/517 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

2. 发明授权

US08278698B2 Nonvolatile memory device and method of forming the same 失效
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US08278698B2
公开(公告)日：2012-10-02
申请号：US12703066
申请日：2010-02-09
申请人： Toshiro Nakanishi , Chanjin Park , Siyoung Choi , Bonyoung Koo
发明人： Toshiro Nakanishi , Chanjin Park , Siyoung Choi , Bonyoung Koo
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/11565
摘要： A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region.
摘要翻译：非易失性存储器件包括器件隔离图案，电荷陷阱层和多个字线。器件隔离图案限定半导体衬底中的有源区并沿第一方向延伸。电荷陷阱层覆盖有源区和器件隔离图案。电荷陷阱层上的字线穿过有源区并沿第二方向延伸。设置在字线和有源区彼此交叉的第一区域中的电荷陷阱层与设置在围绕第一区域的第二区域中的电荷陷阱层具有不同的氮含量比。

3. 发明授权

US09570670B2 Magnetic device and method of fabricating the same 有权
标题翻译：磁性装置及其制造方法
公开(公告)号：US09570670B2
公开(公告)日：2017-02-14
申请号：US13763464
申请日：2013-02-08
申请人： ChanJin Park , Woojin Kim , Hyungjoon Kwon , Soonoh Park , Jongchul Park , Sechung Oh
发明人： ChanJin Park , Woojin Kim , Hyungjoon Kwon , Soonoh Park , Jongchul Park , Sechung Oh
IPC分类号： H01L43/02 , H01L43/08 , H01L43/12
CPC分类号： H01L43/02 , G11C11/1659 , H01L43/08 , H01L43/12
摘要： Provided are a magnetic memory device and a method of fabricating the same. The device may include a magnetic tunnel junction including a lower magnetic structure, an upper magnetic structure, and a tunnel barrier interposed therebetween. The tunnel barrier may have a width greater than that of the lower magnetic structure.
摘要翻译：提供一种磁存储器件及其制造方法。该装置可以包括磁性隧道结，其包括下部磁性结构，上部磁性结构和插入其间的隧道屏障。隧道势垒可以具有大于下部磁性结构的宽度的宽度。

4. 发明申请

US20160359012A1 SEMICONDUCTOR DEVICE BLOCKING LEAKAGE CURRENT AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件阻塞漏电流及其形成方法
公开(公告)号：US20160359012A1
公开(公告)日：2016-12-08
申请号：US15053842
申请日：2016-02-25
申请人： HYUN-KWAN YU , Kooktae Kim , Chanjin Park , Dongsuk Shin , Youngdal Lim , Sahwan Hong
发明人： HYUN-KWAN YU , Kooktae Kim , Chanjin Park , Dongsuk Shin , Youngdal Lim , Sahwan Hong
IPC分类号： H01L29/49 , H01L29/16 , H01L27/092 , H01L29/165 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/161
CPC分类号： H01L29/4991 , H01L21/7682 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L27/0886 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/7848
摘要： A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.
摘要翻译：半导体器件包括设置在器件隔离层上的栅极组件，设置在栅极组件的侧表面上的栅极间隔件，设置在栅极间隔物上的接触组件，设置在器件隔离层和接触组件之间的气隙，以及设置在所述栅极间隔物和所述气隙之间的第一间隔物封盖层。第一间隔物覆盖层相对于栅极间隔物具有蚀刻选择性。

5. 发明授权

US08697498B2 Methods of manufacturing three dimensional semiconductor memory devices using sub-plates 有权
标题翻译：使用子板制造三维半导体存储器件的方法
公开(公告)号：US08697498B2
公开(公告)日：2014-04-15
申请号：US13284435
申请日：2011-10-28
申请人： Byong-hyun Jang , Dongchul Yoo , Chanjin Park , Hanmei Choi
发明人： Byong-hyun Jang , Dongchul Yoo , Chanjin Park , Hanmei Choi
IPC分类号： H01L21/82 , H01L21/00
CPC分类号： H01L21/762 , H01L21/76224 , H01L27/1157 , H01L27/11582
摘要： A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.
摘要翻译：可以通过在板堆叠结构中形成至少一个沟槽来形成制造三维（3D）半导体存储器件的方法，以在形成多个垂直有源图案之间将板堆叠结构分成多个子板堆叠结构在板堆叠结构中和从板堆叠结构的阶梯结构的成形垫。

6. 发明授权

US09536895B2 Methods of fabricating three-dimensional semiconductor devices 有权
标题翻译：制造三维半导体器件的方法
公开(公告)号：US09536895B2
公开(公告)日：2017-01-03
申请号：US14657849
申请日：2015-03-13
申请人： Changhyun Lee , Chanjin Park , Byoungkeun Son , Sung-Il Chang
发明人： Changhyun Lee , Chanjin Park , Byoungkeun Son , Sung-Il Chang
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/0649 , H01L29/7926
摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
摘要翻译：三维半导体器件包括下结构的上结构，上结构包括导电图案，通过上结构连接到下结构的半导体图案，以及半导体图案和上结构之间的绝缘间隔物，底部绝缘间隔物的表面位于等于或高于下部结构的最上表面的垂直水平。

7. 发明授权

US08824184B2 Semiconductor memory devices 有权
标题翻译：半导体存储器件
公开(公告)号：US08824184B2
公开(公告)日：2014-09-02
申请号：US13587476
申请日：2012-08-16
申请人： Ingyu Baek , Chanjin Park , Hyunsu Ju
发明人： Ingyu Baek , Chanjin Park , Hyunsu Ju
IPC分类号： G11C5/02 , G11C8/14 , G11C7/18 , G11C5/06
CPC分类号： G11C5/025 , G11C5/063 , G11C7/18 , G11C8/14 , H01L27/228 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： A semiconductor memory device includes a stacked structure including a plurality of wordline structures sequentially stacked that each include: a plurality of wordlines with sidewalls and extending in a first direction on the substrate, and a connecting pad extending in a second direction on the substrate and being connected in common to the plurality of wordlines. A plurality of interconnections at a height over the substrate are connected to the connecting pads of the wordline structures, respectively. The device further includes bitlines substantially vertical to a top surface of the substrate and crossing one of the sidewalls of the plurality of wordlines, and memory elements between the bitlines and the plurality of wordlines, respectively. A length of the connecting pad in the second direction is substantially equal to a product of a minimum pitch between the interconnections and a stack number of one of the plurality of wordlines.
摘要翻译：半导体存储器件包括堆叠结构，其包括顺序层叠的多个字线结构，每个字线包括：具有侧壁并在衬底上沿第一方向延伸的多个字线，以及在衬底上沿第二方向延伸的连接焊盘，与多个字线共同连接。在衬底上的高度处的多个互连分别连接到字线结构的连接焊盘。该装置还包括基本上垂直于衬底的顶表面并且跨越多个字线的侧壁中的一个以及位线和多个字线之间的存储元件的位线。连接焊盘在第二方向上的长度基本上等于互连之间的最小间距和多个字线之一的堆叠数的乘积。

8. 发明授权

US08377817B2 Three dimensional semiconductor memory device and method of manufacturing the same 有权
公开(公告)号：US08377817B2
公开(公告)日：2013-02-19
申请号：US13173304
申请日：2011-06-30
申请人： Chanjin Park , Kihyun Hwang , Dongchul Yoo , Junkyu Yang , Gyungjin Min , Yoochul Kong , Hanmei Choi
发明人： Chanjin Park , Kihyun Hwang , Dongchul Yoo , Junkyu Yang , Gyungjin Min , Yoochul Kong , Hanmei Choi
IPC分类号： H01L21/4763
CPC分类号： H01L29/788 , H01L23/5384 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

9. 发明申请

US20120112264A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20120112264A1
公开(公告)日：2012-05-10
申请号：US13290425
申请日：2011-11-07
申请人： Changhyun LEE , Chanjin Park , Byoungkeun Son , Sung-Il Chang
发明人： Changhyun LEE , Chanjin Park , Byoungkeun Son , Sung-Il Chang
IPC分类号： H01L29/792 , H01L27/06
CPC分类号： H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/0649 , H01L29/7926
摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
摘要翻译：三维半导体器件包括下结构的上结构，上结构包括导电图案，通过上结构连接到下结构的半导体图案，以及半导体图案和上结构之间的绝缘间隔物，底部绝缘间隔物的表面位于等于或高于下部结构的最上表面的垂直水平。

10. 发明申请

US20170110474A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20170110474A1
公开(公告)日：2017-04-20
申请号：US15392521
申请日：2016-12-28
申请人： CHANGHYUN LEE , CHANJIN PARK , BYOUNGKEUN SON , SUNG-IL CHANG
发明人： CHANGHYUN LEE , CHANJIN PARK , BYOUNGKEUN SON , SUNG-IL CHANG
IPC分类号： H01L27/11582 , H01L29/792 , H01L29/06
CPC分类号： H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/0649 , H01L29/7926
摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

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