专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08377817B2 Three dimensional semiconductor memory device and method of manufacturing the same 有权
公开(公告)号：US08377817B2
公开(公告)日：2013-02-19
申请号：US13173304
申请日：2011-06-30
申请人： Chanjin Park , Kihyun Hwang , Dongchul Yoo , Junkyu Yang , Gyungjin Min , Yoochul Kong , Hanmei Choi
发明人： Chanjin Park , Kihyun Hwang , Dongchul Yoo , Junkyu Yang , Gyungjin Min , Yoochul Kong , Hanmei Choi
IPC分类号： H01L21/4763
CPC分类号： H01L29/788 , H01L23/5384 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

2. 发明申请

US20120001345A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120001345A1
公开(公告)日：2012-01-05
申请号：US13173304
申请日：2011-06-30
申请人： Chanjin Park , Kihyun Hwang , Dongchul Yoo , Junkyu Yang , Gyungjin Min , Yoochul Kong , Hanmei Choi
发明人： Chanjin Park , Kihyun Hwang , Dongchul Yoo , Junkyu Yang , Gyungjin Min , Yoochul Kong , Hanmei Choi
IPC分类号： H01L23/48 , H01L21/306 , H01L21/768
CPC分类号： H01L29/788 , H01L23/5384 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.
摘要翻译：提供三维半导体器件。该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案和封堵图案，其中保护层图案由中间图案分离。

3. 发明申请

US20110233648A1 Three-Dimensional Semiconductor Memory Devices And Methods Of Fabricating The Same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20110233648A1
公开(公告)日：2011-09-29
申请号：US13072078
申请日：2011-03-25
申请人： Kwang Soo Seol , Chanjin Park , Kihyun Hwang , Hanmei Choi , Dongchul Yoo , Sunghoi Hur , Wansik Hwang , Toshiro Nakanishi , Kwangmin Park , Juyul Lee
发明人： Kwang Soo Seol , Chanjin Park , Kihyun Hwang , Hanmei Choi , Dongchul Yoo , Sunghoi Hur , Wansik Hwang , Toshiro Nakanishi , Kwangmin Park , Juyul Lee
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/42348 , H01L21/32137 , H01L27/0688 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/511 , H01L29/517 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
摘要翻译：三维半导体存储器件及其制造方法。三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。

4. 发明授权

US09536970B2 Three-dimensional semiconductor memory devices and methods of fabricating the same 有权
公开(公告)号：US09536970B2
公开(公告)日：2017-01-03
申请号：US13072078
申请日：2011-03-25
申请人： Kwang Soo Seol , Chanjin Park , Kihyun Hwang , Hanmei Choi , Dongchul Yoo , Sunghoi Hur , Wansik Hwang , Toshiro Nakanishi , Kwangmin Park , Juyul Lee
发明人： Kwang Soo Seol , Chanjin Park , Kihyun Hwang , Hanmei Choi , Dongchul Yoo , Sunghoi Hur , Wansik Hwang , Toshiro Nakanishi , Kwangmin Park , Juyul Lee
IPC分类号： H01L29/792 , H01L29/423 , H01L21/3213 , H01L27/06 , H01L27/115 , H01L29/51
CPC分类号： H01L29/42348 , H01L21/32137 , H01L27/0688 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/511 , H01L29/517 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

5. 发明授权

US08697498B2 Methods of manufacturing three dimensional semiconductor memory devices using sub-plates 有权
标题翻译：使用子板制造三维半导体存储器件的方法
公开(公告)号：US08697498B2
公开(公告)日：2014-04-15
申请号：US13284435
申请日：2011-10-28
申请人： Byong-hyun Jang , Dongchul Yoo , Chanjin Park , Hanmei Choi
发明人： Byong-hyun Jang , Dongchul Yoo , Chanjin Park , Hanmei Choi
IPC分类号： H01L21/82 , H01L21/00
CPC分类号： H01L21/762 , H01L21/76224 , H01L27/1157 , H01L27/11582
摘要： A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.
摘要翻译：可以通过在板堆叠结构中形成至少一个沟槽来形成制造三维（3D）半导体存储器件的方法，以在形成多个垂直有源图案之间将板堆叠结构分成多个子板堆叠结构在板堆叠结构中和从板堆叠结构的阶梯结构的成形垫。

6. 发明申请

US20150372005A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20150372005A1
公开(公告)日：2015-12-24
申请号：US14708477
申请日：2015-05-11
申请人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
发明人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
IPC分类号： H01L27/115 , H01L45/00 , H01L23/528 , H01L27/24
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.
摘要翻译：一种三维半导体存储器件，包括在基板上的外围电路结构，外围电路结构上的水平有源层，设置在水平有源层上的堆叠，包括多个电极，垂直穿过堆叠的垂直结构，源区域，以及水平有源层中的拾取区域。水平有源层包括顺序堆叠在外围电路结构上的第一，第二和第三有源半导体层。掺杂第一和第三有源半导体层分别具有高和低杂质浓度，第二有源半导体层包括杂质扩散抑制材料。

7. 发明授权

US10685972B2 Semiconductor memory devices and methods for fabricating the same 有权
公开(公告)号：US10685972B2
公开(公告)日：2020-06-16
申请号：US15514239
申请日：2014-09-26
申请人： Sunggil Kim , Phil Ouk Nam , Gukhyon Yon , Sunghae Lee , Woojin Jang , Dongchul Yoo , Hunhyeong Lim , Junggeun Jee , Kihyun Hwang
发明人： Sunggil Kim , Phil Ouk Nam , Gukhyon Yon , Sunghae Lee , Woojin Jang , Dongchul Yoo , Hunhyeong Lim , Junggeun Jee , Kihyun Hwang
IPC分类号： H01L27/11582 , H01L27/11568 , H01L21/28 , H01L27/115 , H01L49/02 , H01L21/02 , H01L21/311 , H01L27/1157 , H01L29/10
摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

8. 发明授权

US09997530B2 Three-dimensional semiconductor memory device and method of fabricating the same 有权
公开(公告)号：US09997530B2
公开(公告)日：2018-06-12
申请号：US14708477
申请日：2015-05-11
申请人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
发明人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
IPC分类号： H01L27/11582 , H01L27/11573 , H01L27/24 , H01L27/11578 , H01L27/11556 , H01L27/11575 , H01L45/00
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

9. 发明授权

US09960046B2 Methods of manufacturing semiconductor device having a blocking insulation layer 有权
公开(公告)号：US09960046B2
公开(公告)日：2018-05-01
申请号：US15609099
申请日：2017-05-31
申请人： Jung Ho Kim , Bio Kim , Jaeyoung Ahn , Dongchul Yoo
发明人： Jung Ho Kim , Bio Kim , Jaeyoung Ahn , Dongchul Yoo
IPC分类号： H01L21/28 , H01L27/1157 , H01L27/11582 , H01L21/02
CPC分类号： H01L21/28282 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L27/1157 , H01L27/11582
摘要： A method of manufacturing a semiconductor device includes forming insulation layers and sacrificial layers that are alternately and repeatedly stacked on top of each other a substrate, forming a vertical hole that penetrates the insulation layers and the sacrificial layers, and forming a vertical channel structure in the vertical hole. The forming the vertical channel structure includes forming a blocking insulation layer, a charge storage layer, a tunnel insulation layer, and a semiconductor pattern. The forming the blocking insulation layer includes forming a first oxidation target layer, oxidizing the first oxidation target layer to form a first sub-blocking layer, and forming a second sub-blocking layer. The first sub-blocking layer is formed between the second sub-blocking layer and an inner sidewall of the vertical hole.

10. 发明授权

US09397114B2 Methods of fabricating three-dimensional semiconductor memory devices 有权
标题翻译：制造三维半导体存储器件的方法
公开(公告)号：US09397114B2
公开(公告)日：2016-07-19
申请号：US13475023
申请日：2012-05-18
申请人： Jumi Yun , Kwangmin Park , Dongchul Yoo , Byong-hyun Jang
发明人： Jumi Yun , Kwangmin Park , Dongchul Yoo , Byong-hyun Jang
IPC分类号： H01L27/00 , H01L21/00 , H01L27/115 , H01L21/31 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/31 , H01L29/7926
摘要： Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.
摘要翻译：制造三维半导体存储器件的方法包括：将具有绝缘层和牺牲层的叠层结构形成在衬底上的层叠层，形成将板堆结构分成多个模具结构的第一和第二沟槽，第一沟槽位于第二沟槽，在第一和第二沟槽中形成第一垂直绝缘隔板，形成穿透模具结构并与第一和第二沟槽隔开的半导体图案，从第二沟槽移除第一垂直绝缘隔板以暴露牺牲层，去除所述牺牲层由所述第二沟槽暴露以形成部分地暴露所述半导体图案和所述第一垂直绝缘隔板的凹部区域，以及在所述凹部区域中形成导电图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式