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1. 发明授权

US08097500B2 Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device 有权
标题翻译：用于制造高性能带边互补金属氧化物半导体器件的方法和装置
公开(公告)号：US08097500B2
公开(公告)日：2012-01-17
申请号：US12013846
申请日：2008-01-14
申请人： Takashi Ando , Eduard A. Cartier , Changhwan Choi , Elizabeth A. Duch , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , James Pan , Vamsi K. Paruchuri
发明人： Takashi Ando , Eduard A. Cartier , Changhwan Choi , Elizabeth A. Duch , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , James Pan , Vamsi K. Paruchuri
IPC分类号： H01L21/00
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L27/1203 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.
摘要翻译：在一个实施例中，本发明是用于制造高性能带边互补金属氧化物半导体器件的方法和装置。用于制造互补金属氧化物半导体器件的方法的一个实施例包括使用栅极第一工艺制造n型金属氧化物半导体器件，以及使用栅极最后工艺制造p型金属氧化物半导体器件。

2. 发明申请

US20090181505A1 METHOD AND APPARATUS FOR FABRICATING A HIGH-PERFORMANCE BAND-EDGE COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造高性能带边补充金属氧化物半导体器件的方法和装置
公开(公告)号：US20090181505A1
公开(公告)日：2009-07-16
申请号：US12013846
申请日：2008-01-14
申请人： Takashi Ando , Eduard A. Cartier , Changhwan Choi , Elizabeth A. Duch , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , James Pan , Vamsi K. Paruchuri
发明人： Takashi Ando , Eduard A. Cartier , Changhwan Choi , Elizabeth A. Duch , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , James Pan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L27/1203 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.
摘要翻译：在一个实施例中，本发明是用于制造高性能带边互补金属氧化物半导体器件的方法和装置。用于制造互补金属氧化物半导体器件的方法的一个实施例包括使用栅极第一工艺制造n型金属氧化物半导体器件，以及使用栅极最后工艺制造p型金属氧化物半导体器件。

3. 发明授权

US08772169B2 Technique for controlling trench profile in semiconductor structures 有权
公开(公告)号：US08772169B2
公开(公告)日：2014-07-08
申请号：US12109302
申请日：2008-04-24
申请人： Hui Chen , Qi Wang , Briant Harward , James Pan
发明人： Hui Chen , Qi Wang , Briant Harward , James Pan
IPC分类号： H01L21/311
摘要： A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

4. 发明授权

US08669623B2 Structure related to a thick bottom dielectric (TBD) for trench-gate devices 有权
标题翻译：与沟槽栅极器件的厚底部电介质（TBD）有关的结构
公开(公告)号：US08669623B2
公开(公告)日：2014-03-11
申请号：US12870600
申请日：2010-08-27
申请人： James Pan , Christopher Lawrence Rexer
发明人： James Pan , Christopher Lawrence Rexer
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/8725
摘要： A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
摘要翻译：包括屏蔽栅极的半导体结构如下形成。使用掩模在半导体区域中形成多个沟槽。掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。沿每个沟槽的底部形成厚底部电介质（TBD）。第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。屏蔽电极形成在每个沟槽的底部。在每个沟槽中的屏蔽电极之上形成栅电极。

5. 发明授权

US08541840B2 Structure and method for semiconductor power devices 有权
标题翻译：半导体功率器件的结构和方法
公开(公告)号：US08541840B2
公开(公告)日：2013-09-24
申请号：US13028054
申请日：2011-02-15
申请人： James Pan
发明人： James Pan
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/0635 , H01L29/1087 , H01L29/4175 , H01L29/78624
摘要： A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.
摘要翻译：半导体器件包括在衬底上的绝缘体上半导体区域。绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。因此，MOS晶体管的漏极也用作双极晶体管的发射极。此外，栅极和基极通过电阻元件耦合。

6. 发明授权

US08329538B2 Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein 有权
标题翻译：屏蔽栅沟槽FET，其中具有低k电介质的电极间电介质
公开(公告)号：US08329538B2
公开(公告)日：2012-12-11
申请号：US13083253
申请日：2011-04-08
申请人： James Pan , James J. Murphy
发明人： James Pan , James J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66727 , H01L29/66734
摘要： A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
摘要翻译：一种用于形成屏蔽栅极沟道场效应晶体管（FET）的方法包括在半导体区域中形成沟槽，在每个沟槽的底部形成屏蔽电极，并形成在屏蔽电极上延伸的电极间电介质（IED）。 IED可以包括低k电介质。该方法还包括在IED上的每个沟槽的上部形成栅电极。

7. 发明申请

US20120292676A1 Novel Very Fast Optic Nonvolatile Memory with Alternative Carrier Lifetimes and Bandgap Energies, Optic Random Access, and Mirrored "Fly-back" Configurations 审中-公开
标题翻译：具有替代载波寿命和带隙能量的新型非常快速的非易失性存储器，光学随机存取和镜像“反馈”配置
公开(公告)号：US20120292676A1
公开(公告)日：2012-11-22
申请号：US13113048
申请日：2011-05-21
申请人： James Pan
发明人： James Pan
IPC分类号： H01L31/113
CPC分类号： G11C13/047
摘要： The present invention is for a fast optic nonvolatile memory cell (FONM) that operates with a speed >1000000 times faster than the commercially available FLASH memory. The information (or charges) can be entered into the FONM cell by switching on a built-in laser or LED (Light Emitting Diode). Excited by the lights, and driven by electric fields, the regions of low carrier lifetimes thermally generate excess electrons or positive charges to fill the storage gaps or interfaces. To detect the stored information, two BJTs (Bipolar Junction Transistors) are arranged in a mirrored configuration—with alternative regions of high or low carrier lifetimes and bandgap energies. By comparing the BJT “fly-back” characteristics a voltage difference can be detected as a signal of whether the information is stored or not stored.
摘要翻译：本发明用于快速光学非易失性存储单元（FONM），其以比市售的闪速存储器快1000000倍的速度运行。通过打开内置激光或LED（发光二极管）可以将信息（或电荷）输入到FONM单元。由光激发，由电场驱动，低载流子寿命的区域会产生过量的电子或正电荷，以填充储存间隙或界面。为了检测存储的信息，两个BJT（双极结晶体管）被布置成镜像配置 - 具有高或低载波寿命和带隙能量的替代区域。通过比较BJT回扫特性，可以检测电压差是否存储信息或不存储信息。

8. 发明申请

US20120273884A1 Superjunction Structures for Power Devices and Methods of Manufacture 有权
标题翻译：功率器件的超结构和制造方法
公开(公告)号：US20120273884A1
公开(公告)日：2012-11-01
申请号：US13095690
申请日：2011-04-27
申请人： Joseph A. Yedinak , Christopher L. Rexer , Mark L. Rinehimer , Praveen Muraleedharan Shenoy , Jaegil Lee , Hamza Yilmaz , Chongman Yun , Dwayne S. Reichl , James Pan , Rodney S. Ridley, SR. , Harold Heidenreich
发明人： Joseph A. Yedinak , Christopher L. Rexer , Mark L. Rinehimer , Praveen Muraleedharan Shenoy , Jaegil Lee , Hamza Yilmaz , Chongman Yun , Dwayne S. Reichl , James Pan , Rodney S. Ridley, SR. , Harold Heidenreich
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0878 , H01L29/045 , H01L29/0634 , H01L29/0646 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/42372 , H01L29/4238 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
摘要翻译：功率器件包括半导体区域，该半导体区域又包括多个交替布置的第一和第二导电类型的柱。第二导电类型的多个柱中的每一个还包括沿着第二导电类型的柱的深度彼此顶部布置的多个第二导电类型的注入区，以及填充有第二导电类型的半导体材料的沟槽部在第二导电类型的多个植入区域的正上方。

9. 发明授权

US08273703B2 IL-17 receptor-like polypeptides and therapeutic uses thereof 有权
标题翻译： IL-17受体样多肽及其治疗用途
公开(公告)号：US08273703B2
公开(公告)日：2012-09-25
申请号：US11529324
申请日：2006-09-29
申请人： Jian Chen , Ellen Filvaroff , Sherman Fong , Dorothy French , Audrey Goddard , Paul J. Godowski , J. Christopher Grimaldi , Austin L. Gumey , Kenneth J. Hillan , Sarah G. Hymowitz , Hanzhong Li , James Pan , Melissa A. Starovasnik , Daniel Tumas , Menno Van Lookeren , Richard Vandlen , Colin K. Watanabe , P. Mickey Williams , William I. Wood , Daniel G. Yansura
发明人： Jian Chen , Ellen Filvaroff , Sherman Fong , Dorothy French , Audrey Goddard , Paul J. Godowski , J. Christopher Grimaldi , Austin L. Gumey , Kenneth J. Hillan , Sarah G. Hymowitz , Hanzhong Li , James Pan , Melissa A. Starovasnik , Daniel Tumas , Menno Van Lookeren , Richard Vandlen , Colin K. Watanabe , P. Mickey Williams , William I. Wood , Daniel G. Yansura
IPC分类号： A61K38/16
CPC分类号： C07K16/244 , A61K38/00 , C07H21/04 , C07K14/54 , C07K14/7155 , C07K2317/21 , C07K2317/24 , C07K2317/35 , C07K2317/54 , C07K2317/55 , C07K2317/62 , G01N33/505 , G01N33/564 , G01N33/574 , G01N33/57407 , G01N33/57423 , G01N33/57438 , G01N33/57492 , G01N2333/54 , G01N2333/7155
摘要： The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.
摘要翻译：本发明涉及与IL-17，IL-17受体和编码那些多肽的核酸分子具有序列同一性的新型多肽。本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明的多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法发明。本文还提供了治疗退行性软骨疾病和其它炎性疾病的方法。

10. 发明授权

US08067229B2 UCP4 有权
公开(公告)号：US08067229B2
公开(公告)日：2011-11-29
申请号：US11265966
申请日：2005-11-03
申请人： Sean Adams , James Pan , Alan Zhong
发明人： Sean Adams , James Pan , Alan Zhong
IPC分类号： C12N15/12 , C12N15/63 , C12N5/10 , C12N5/16
CPC分类号： C07K14/4702 , A61K38/00 , A61K48/00 , C07K14/47 , C07K2319/00
摘要： The present invention is directed to novel polypeptides having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.
摘要翻译：本发明涉及与某些人解偶联蛋白（“UCP”）和编码那些多肽的核酸分子具有同源性的新型多肽。本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明多肽的嵌合多肽分子，与本发明的多肽结合的抗体，以及本发明多肽的制备方法发明。

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