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1. 发明申请

US20130163343A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20130163343A1
公开(公告)日：2013-06-27
申请号：US13600541
申请日：2012-08-31
申请人： Chang Won YANG , Hwang Huh , Myung jin Park , Chang Hyuk Lee
发明人： Chang Won YANG , Hwang Huh , Myung jin Park , Chang Hyuk Lee
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26
摘要： The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.
摘要翻译：半导体存储器件包括存储单元阵列，其包括耦合在公共源极线和多个位线之间的多个单元串，读出存储在选择的存储单元中的数据的外围电路，将电压提供给公共源极线和参考电压，从而在执行读取操作时输出检测信号;以及控制电路，其控制外围电路，以便根据所述控制电路来调整感测操作次数，从而执行读取操作检测信号。

2. 发明申请

US20080279034A1 DATA OUTPUT CIRCUIT OF SYNCHRONOUS MEMORY DEVICE 有权
标题翻译：同步存储器件的数据输出电路
公开(公告)号：US20080279034A1
公开(公告)日：2008-11-13
申请号：US12112149
申请日：2008-04-30
申请人： Chang Hyuk Lee
发明人： Chang Hyuk Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069
摘要： A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.
摘要翻译：包括具有N位预取功能的多个管线的同步存储装置的数据输出电路。每个流水线装置包括用于切换N位数据的输出路径的数据切换部分; 第一数据选择部分，用于接收N位数据的一半，并响应于第一控制信号输出一半; 第二数据选择部分，用于接收N位数据的另一半，并响应于第一控制信号输出另一半; 第一移位器，用于在接收到第一控制信号之后输出第一时间延迟的第二控制信号; 以及第二移位器，用于接收从第二数据选择部分输出的数据，并响应于第二控制信号以第一时间的延迟输出数据。

3. 发明授权

US07447090B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07447090B2
公开(公告)日：2008-11-04
申请号：US11647400
申请日：2006-12-29
申请人： Chang-Hyuk Lee
发明人： Chang-Hyuk Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1042 , G11C7/22 , G11C2207/065
摘要： A semiconductor memory device includes: a first bit line sense amplifier array for amplifying a data input to a first bit line pair coupled to cells; a second bit line sense amplifier array for amplifying a data input to a second bit line pair coupled to the cells; and a control unit for activating one of the first and second bit line sense amplifier arrays and, after a predetermined time, for activating the other bit line sense amplifier array in response to an active signal and a column address information signal.
摘要翻译：半导体存储器件包括：第一位线读出放大器阵列，用于放大输入到耦合到单元的第一位线对的数据; 第二位线读出放大器阵列，用于放大输入到耦合到所述单元的第二位线对的数据; 以及控制单元，用于激活第一和第二位线读出放大器阵列之一，并且在预定时间之后，响应于有效信号和列地址信息信号激活另一位线读出放大器阵列。

4. 发明授权

US07283421B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07283421B2
公开(公告)日：2007-10-16
申请号：US11323509
申请日：2005-12-29
申请人： Chang-Hyuk Lee
发明人： Chang-Hyuk Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C11/4076 , G11C11/4082
摘要： The present invention provides a semiconductor memory device for reducing a power consumption. A semiconductor memory device includes a command decoding unit for decoding a plurality of commands; a driving signal generation unit for generating a plurality of driving signals synchronized with Nth clocks of an internal clock from an activation timing of a CAS signal generated by the command decoding unit, wherein N is an even integer number; an address delay unit for receiving an internal address in response to the CAS signal and for delaying the internal address signal by synchronizing the internal address with the plurality of driving signals; and a data access block for performing a data access in response to the delayed internal address.
摘要翻译：本发明提供一种用于降低功耗的半导体存储器件。半导体存储器件包括用于对多个命令进行解码的命令解码单元; 驱动信号生成单元，用于根据由命令解码单元生成的CAS信号的激活定时产生与内部时钟的第N个时钟同步的多个驱动信号，其中N是偶数整数; 地址延迟单元，用于响应于CAS信号接收内部地址，并通过使内部地址与多个驱动信号同步来延迟内部地址信号; 以及用于响应于延迟的内部地址执行数据访问的数据访问块。

5. 发明申请

US20070070713A1 DATA OUTPUT DEVICE OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件的数据输出器件
公开(公告)号：US20070070713A1
公开(公告)日：2007-03-29
申请号：US11322078
申请日：2005-12-30
申请人： Chang-Hyuk Lee
发明人： Chang-Hyuk Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/20 , G11C11/4072 , G11C11/4096
摘要： There is provided a data output device for stably operating in a high frequency circumstance. The data output device includes a selection unit for receiving a second address information signal to directly output or inversely output the received signal as a third address information signal in response to a first address information signal; a pipe output control unit for generating a plurality of pipe output control signals; a plurality of pipe latch units for storing a global data in response to a pipe input control signal and aligning the stored data in response to the first to the third address information signals, thereby outputting the aligned data synchronized by the pipe output control signals; and a data driving unit for outputting the aligned data as an external data in response to a first and a second DLL output clock.
摘要翻译：提供了用于在高频环境中稳定操作的数据输出装置。数据输出装置包括：选择单元，用于响应于第一地址信息信号，接收第二地址信息信号，以直接输出或反向输出接收信号作为第三地址信息信号; 管输出控制单元，用于产生多个管输出控制信号; 多个管锁定单元，用于响应于管道输入控制信号存储全局数据，并响应于第一至第三地址信息信号对存储的数据进行排列，由此输出由管道输出控制信号同步的校准数据; 以及数据驱动单元，用于响应于第一和第二DLL输出时钟输出对准的数据作为外部数据。

6. 发明授权

US07184325B2 Input circuit for memory device 有权
标题翻译：存储器件的输入电路
公开(公告)号：US07184325B2
公开(公告)日：2007-02-27
申请号：US11092382
申请日：2005-03-29
申请人： Chang Hyuk Lee
发明人： Chang Hyuk Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block column address is provided. In particular, a data input apparatus improving a data processing speed by advancing an operation time point of a data bus writer is provided.
摘要翻译：公开了一种用于半导体存储器件的输入电路。提供了通过使用1时钟位移块列地址来控制已经通过数据输入缓冲器的数据的传输路径的输入电路。特别地，提供了通过推进数据总线写入器的操作时间点来提高数据处理速度的数据输入装置。

7. 发明申请

US20060285425A1 Data output circuit of synchronous memory device 有权
公开(公告)号：US20060285425A1
公开(公告)日：2006-12-21
申请号：US11451109
申请日：2006-06-12
申请人： Chang Hyuk Lee
发明人： Chang Hyuk Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069
摘要： A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.

8. 发明授权

US06333666B2 Antifuse circuit being programmable by using no connection pin 失效
标题翻译：防漏电路可通过不使用连接引脚进行编程
公开(公告)号：US06333666B2
公开(公告)日：2001-12-25
申请号：US09737854
申请日：2000-12-18
申请人： Phil-Jung Kim , Jae-Kyung Wee , Chang-Hyuk Lee , Jin-Keun Oh , Jae-Seok Park , Oh-Won Kwon , Ho-Youb Cho
发明人： Phil-Jung Kim , Jae-Kyung Wee , Chang-Hyuk Lee , Jin-Keun Oh , Jae-Seok Park , Oh-Won Kwon , Ho-Youb Cho
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation. For the purpose, the antifuse circuit includes a power-up detecting circuit for generating a power stabilization signal by detecting a supply voltage; a power-up pulse circuit for generating a first and a second control signal in response to the power stabilization signal; an antifuse programming circuit for, under the control of the first and the second control signals, detecting whether an antifuse element is programmed or not, latching the result of the detection and programming the antifuse element in response to an external high voltage and a precharge signal; a pin for receiving the external high voltage so as to program the antifuse element; a pad for providing the external high voltage to the inside of the chip; and a diode for supplying the external high voltage to the antifuse programming circuit and preventing a voltage of the antifuse programming circuit from being provided to the pin.
摘要翻译：反熔丝电路通过使用不用于芯片操作的NC引脚向反熔丝编程电路提供稳定的高电压。为此，反熔丝电路包括用于通过检测电源电压来产生功率稳定信号的上电检测电路; 上电脉冲电路，用于响应于所述功率稳定信号产生第一和第二控制信号; 反熔丝编程电路，用于在第一和第二控制信号的控制下检测反熔丝元件是否被编程，锁存检测结果并响应于外部高电压和预充电信号编程反熔丝元件 ; 用于接收外部高电压以便对反熔丝元件进行编程的引脚; 用于向芯片内部提供外部高电压的焊盘; 以及用于将外部高电压提供给反熔丝编程电路并防止反熔丝编程电路的电压被提供给引脚的二极管。

9. 发明授权

US06329694B1 Semiconductor device with ESD protective circuit 有权
标题翻译：具有ESD保护电路的半导体器件
公开(公告)号：US06329694B1
公开(公告)日：2001-12-11
申请号：US09342102
申请日：1999-06-29
申请人： Chang Hyuk Lee , Jae Goan Jeong
发明人： Chang Hyuk Lee , Jae Goan Jeong
IPC分类号： H01L2974
CPC分类号： H01L27/0266 , H02H9/046
摘要： A semiconductor device with an electrostatic discharge (ESD) protective circuit is disclosed. In this semiconductor device with an ESD protective circuit, an n-well guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer. The n-well guard ring is strapped to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, and thus a PNPN path is formed toward the PMOS transistor at a positive mode of the ground voltage. Therefore, the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device. Further the layout area is reduced, and thus, the characteristics and the reliability of the semiconductor device are improved.
摘要翻译：公开了一种具有静电放电（ESD）保护电路的半导体器件。在具有ESD保护电路的该半导体器件中，在数据输入缓冲器的NMOS场晶体管周围或数据输出缓冲器的NMOS晶体管周围形成n阱保护环。 n阱保护环被连接到PMOS场晶体管的n阱和PMOS晶体管的n阱，因此在接地电压的正模式下朝向PMOS晶体管形成PNPN路径。因此，可以减小NMOS晶体管的阱和PMOS晶体管之间的电阻，从而提高ESD保护电路和闭锁装置的特性。此外，布局面积减小，因此提高了半导体器件的特性和可靠性。

10. 发明授权

US07710797B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07710797B2
公开(公告)日：2010-05-04
申请号：US11819791
申请日：2007-06-29
申请人： Chang-Hyuk Lee
发明人： Chang-Hyuk Lee
IPC分类号： G11C7/00
CPC分类号： G06F13/4086 , G11C7/1048
摘要： A semiconductor memory device stably performs a write operation with reduced current consumption. The semiconductor memory device includes a global data, a control unit, a termination resistor unit, and a storage unit. The global data line transmits data. The control unit generates a global control signal during a read operation or a write operation. The termination resistance unit supplies termination resistance to the global data line in response to the global control signal. The storage unit stores the data transmitted to the global data line while the termination resistance unit is inactivated. A method for driving the semiconductor memory device includes detecting a read operation or a write operation and supplying termination resistance when the read or write operation is detected.
摘要翻译：半导体存储器件以降低的电流消耗稳定地执行写入操作。半导体存储器件包括全局数据，控制单元，终端电阻单元和存储单元。全局数据线传输数据。控制单元在读取操作或写入操作期间产生全局控制信号。终端电阻单元响应全局控制信号向全局数据线提供终端电阻。存储单元存储发送到全局数据线的数据，同时终止电阻单元被停用。一种用于驱动半导体存储器件的方法包括检测读取操作或写入操作，并且当检测到读取或写入操作时提供终止电阻。

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