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    • 1. 发明授权
    • Replacement metal gate semiconductor device formation using low resistivity metals
    • 使用低电阻率金属的替代金属栅极半导体器件形成
    • US08722491B2
    • 2014-05-13
    • US13603726
    • 2012-09-05
    • Chang Seo ParkVimal K. Kamineni
    • Chang Seo ParkVimal K. Kamineni
    • H01L21/8234H01L21/3205H01L21/4763H01L21/336H01L21/44
    • H01L29/401H01L29/66545H01L29/66795
    • Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.
    • 本发明的实施例涉及使用低电阻率金属(例如W)作为替代间隙填充金属形成RMG FinFET半导体器件的方法。 具体地,半导体通常将包括形成在衬底上以形成一个或多个沟槽(例如,短/窄和/或长/宽沟槽/沟道)的一组(例如,一个或多个)电介质叠层。 工作功能层(例如,TiN)将被提供在衬底上(例如,在沟槽中和周围)。 然后可以沉积低电阻金属栅极层(例如,W)(例如通过化学气相沉积)并抛光(例如,经由化学机械抛光)。 此后,可以在抛光之后蚀刻栅极金属层和功函数层,以沿着其底表面在蚀刻的功函数层上方提供具有蚀刻的栅极金属层的沟槽。
    • 10. 发明授权
    • Method for fabricating a gate electrode of a semiconductor device
    • 制造半导体器件的栅电极的方法
    • US06551913B1
    • 2003-04-22
    • US09343480
    • 1999-06-30
    • Hyeon Soo KimChang Seo Park
    • Hyeon Soo KimChang Seo Park
    • H01L213205
    • H01L29/665
    • The present invention relates to a semiconductor technology and more specifically to a method of fabricating a gate electrode of a semiconductor device, where a re-oxidation process that may cause an abnormal oxidation can be eliminated. In a polysilicon/silicide structure or polysilicon/metal structure of gate electrode, a step of etching side parts of gate electrode is performed without any etch mask after gate patterning. Here, the etch can be made by wet or dry etch using an etchant having high selectivity of polysilicon film to a gate oxide film, so that the damaged gate oxide part during the gate patterning is allowed not to make a role of the gate insulating film itself, thereby eliminating the re-oxidation process.
    • 本发明涉及一种半导体技术,更具体地涉及制造可能引起异常氧化的再氧化工艺的半导体器件的栅电极的制造方法。 在栅极电极的多晶硅/硅化物结构或多晶硅/金属结构中,在栅极图案化之后,没有任何蚀刻掩模执行刻蚀栅极的侧面部分的步骤。 这里,可以通过使用具有多晶硅膜对栅极氧化膜的高选择性的蚀刻剂的湿蚀刻或干法蚀刻来进行蚀刻,使得栅极图案化期间损坏的栅极氧化物部分不被起到栅极绝缘膜的作用 本身,从而消除再氧化过程。