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    • 2. 发明授权
    • Semiconductor device and a circuit suitable for use in an intelligent
power switch
    • 半导体器件和适用于智能电源开关的电路
    • US5128730A
    • 1992-07-07
    • US727317
    • 1991-07-02
    • David J. CoeDavid H. PaxmanFranciscus A. C. M. Schoofs
    • David J. CoeDavid H. PaxmanFranciscus A. C. M. Schoofs
    • G05F3/24H01L21/336H01L27/04H01L27/07H01L27/088H01L29/78H03K17/06H03K17/687H03K17/78
    • H01L29/7816H01L27/0727H01L27/088H01L29/7801H01L29/7802H03K17/06H03K17/687H01L29/41766
    • A semiconductor device and a circuit suitable for use in an intelligent power switch include an insulated gate field effect transistor (IGFET) (T2) and a power semiconductor switch (T1). The insulated gate field transistor IGFET (T2) is provided by a semiconductor body (6) which has a first region (7) of one conductivity type adjacent a given surface (6a) of the semiconductor body with the first region (7) forming at least part of a conductive path to a first main electrode of the power semiconductor switch. A second region (8) of the opposite conductivity type is provided within the first region adjacent the given surface (6a) and a third region (11) of the one conductivity type is provided adjacent the given surface (6a) within the second region (8), an area of the second region (8) underlying an insulated gate (14) provided on the given surface (6a) for defining a conduction channel (15) providing a gateable connection between the third region (11) and a fourth region (12) of the one conductivity type. The third and fourth regions (11 and 12) forming the source and drain regions of the IGFET and the second and third regions (8 and 11) together provide a zener diode, a conductive path being provided to the second region remote from the area underlying the insulated gate for reverse-biassing the zener diode. The IGFET may include a synchronous rectifier of a charge pump for providing a gate voltage signal to the power semiconductor switch which may be a power MOSFET (T2).
    • 适用于智能电源开关的半导体器件和电路包括绝缘栅场效应晶体管(IGFET)(T2)和功率半导体开关(T1)。 绝缘栅场效应晶体管IGFET(T2)由半导体本体(6)提供,半导体本体(6)具有与半导体本体的给定表面(6a)相邻的一种导电类型的第一区域(7),第一区域(7)形成在 到功率半导体开关的第一主电极的导电路径的至少一部分。 相邻导电类型的第二区域(8)设置在与给定表面(6a)相邻的第一区域内,并且在第二区域内邻近给定表面(6a)设置一个导电类型的第三区域(11) 8),设置在给定表面(6a)上的绝缘栅极(14)下方的第二区域(8)的区域,用于限定在第三区域(11)和第四区域(11)之间提供可栅极连接的导电通道(15) (12)的一种导电类型。 形成IGFET和第二和第三区域(8和11)的源极和漏极区域的第三和第四区域(11和12)一起提供齐纳二极管,导电路径被提供到远离其下面的区域的第二区域 用于反向偏置齐纳二极管的绝缘栅极。 IGFET可以包括用于向可以是功率MOSFET(T2)的功率半导体开关提供栅极电压信号的电荷泵的同步整流器。
    • 3. 发明授权
    • Semiconductor devices
    • 半导体器件
    • US4881119A
    • 1989-11-14
    • US306243
    • 1989-02-02
    • David H. PaxmanJohn A. G. SlatterDavid J. Coe
    • David H. PaxmanJohn A. G. SlatterDavid J. Coe
    • H01L29/68H01L21/8249H01L27/06H01L27/07H01L29/73
    • H01L29/7302H01L27/0716
    • A semiconductor device includes a bipolar transistor having an emitter region of one conductivity type formed in a base region of the opposite conductivity type, the base region being provided in a collector region of the one conductivity type. A first insulated gate field effect transistor provides a gateable connection to the emitter region of the bipolar transistor while a second insulated gate field effect transistor provides a charge extraction path from the base region when the bipolar transistor is turned off. The first insulated gate field effect transistor includes a further region of the other conductivity type provided in the emitter region, and a source region of the one conductivity type formed in the further region and an insulated gate overlying a channel area comprising at least part of the further region to provide a gateable connection between the emitter region and the source region of the first insulated gate field effect transistor. The second insulated gate field effect transistor having an insulated gate overlying a channel area comprising at least part of the emitter region adjacent the base region to provide a gateable connection between the base region and a source of the second insulated gate field effect transistor.
    • 半导体器件包括双极晶体管,其具有形成在相反导电类型的基极区域中的一种导电类型的发射极区域,该基极区域设置在一种导电类型的集电极区域中。 第一绝缘栅场效应晶体管提供与双极晶体管的发射极区域的可选择连接,而第二绝缘栅场效应晶体管在双极晶体管截止时提供从基极区域的电荷提取路径。 第一绝缘栅场效应晶体管包括设置在发射极区域中的另一导电类型的另一区域,以及形成在另一区域中的一种导电类型的源极区域和覆盖沟道区域的绝缘栅极,该绝缘栅极包括至少部分 以在第一绝缘栅场效应晶体管的发射极区域和源极区域之间提供可选择的连接。 第二绝缘栅场效应晶体管具有覆盖沟道区域的绝缘栅极,该沟道区域包括与基极区域相邻的发射极区域的至少一部分,以在第二绝缘栅场效应晶体管的基极区域和源极之间提供可栅极连接。
    • 8. 发明授权
    • High voltage guard ring with variable width shallow portion
    • 具有可变宽度浅部分的高压保护环
    • US4602266A
    • 1986-07-22
    • US570565
    • 1984-01-13
    • David J. Coe
    • David J. Coe
    • H01L21/331H01L21/822H01L27/04H01L29/06H01L29/73H01L29/74H01L29/76H01L29/772H01L29/78H01L29/861
    • H01L29/0615H01L29/0619H01L29/0692H01L29/0696H01L29/7322H01L29/7811H01L29/7833H01L29/04H01L29/063H01L29/0847H01L29/1004H01L29/1095H01L29/408Y10S257/905
    • At least one annular region (11,12, . . . ) extends around an active device region (10) and is located within the spread of a depletion layer (25) from a reverse-biased p-n junction (20) formed by the device region (10) to increase the breakdown voltage of the junction (20). The device region (10) and/or at least one inner annular region (11,12, . . . ) includes at least one shallower portion (10b,11b, . . . ) which extends laterally outwards from a deep portion (10a,11a,12a, . . . ) and faces the surrounding annular region to change the spacing and depth relationship of these regions. This permits high punch-through voltages to be achieved between the regions (10,11,12, . . . ) while reducing peak fields at the bottom outer corners of the regions (10,11,12, . . . ). Inwardly-extending shallow portions (11c,12c, . . . ) may also be included. The shallow portions (10b,11b,11c,12c . . . ) may extend around the whole of a perimeter of the region or be localized where higher electrostatic fields may occur around the perimeter.
    • 至少一个环形区域(11,12 ...)围绕有源器件区域(10)延伸,并且位于从由器件形成的反向偏置pn结(20)的耗尽层(25)的扩展之内 区域(10)以增加接合部(20)的击穿电压。 装置区域(10)和/或至少一个内部环形区域(11,12 ...)包括至少一个较浅部分(10b,11b ......),其从深部(10a, 11a,12a,...)并且面向周围的环形区域以改变这些区域的间隔和深度关系。 这允许在区域(10,11,12 ...之间)实现高穿透电压,同时减少区域(10,11,12 ...)的底部外角处的峰值场。 还可以包括向内延伸的浅部分(11c,12c,...)。 浅部(10b,11b,11c,12c ...)可以围绕该区域的整个周边延伸,或者被定位在周围周围可能出现较高静电场的位置。
    • 9. 发明授权
    • Insulated-gate field-effect transistors
    • 绝缘栅场效应晶体管
    • US4521795A
    • 1985-06-04
    • US446141
    • 1982-12-02
    • David J. CoeRoyce Lowis
    • David J. CoeRoyce Lowis
    • H01L29/06H01L29/78
    • H01L29/0696H01L29/7806H01L29/7813H01L29/782H01L29/0619H01L29/4236
    • An insulated-gate field-effect transistor which may be of the D-MOS or V-MOS type includes a source region (1) which is surrounded by a second region (2) of opposite conductivity type, itself surrounded by a third region (3) associated with the transistor drain (4). An insulated gate (12) of the transistor is present on a channel area of the second region (2) between the source region (1) and a first part (31) of the third region (3). The third region (3) also has a surface-adjoining second part (32) which is remote from the first part (31) and preferably has a lower doping concentration than the second and source regions (2, 1). An electrode layer (11) which may be the source electrode extends on said second part (32) of the third region (3) and is connected to said second region (2), and there is present between this electrode layer (11) and the second part (32) of the third region (3) a Schottky junction (33) having a lower forward voltage drop than the p-n junction (34) between the second and third regions (2,3). The transistor can have a fast switching speed even when driving inductive loads, since the Schottky junction (33) suppresses minority carrier injection at the forward-biased p-n junction (34) during voltage overswings. Preferably the second part (32) of the third region (3) is laterally bounded by the second region (2) which forms a guard ring for the Schottky junction (33) so maintaining a high blocking voltage capability. In order to further suppress minority carrier injection the electrode layer (11) preferably forms with the second region (2) a Schottky junction around which the source region (1) preferably extends as a guard ring.
    • 可以是D-MOS或V-MOS型的绝缘栅场效应晶体管包括由具有相反导电类型的第二区域(2)包围的源极区域(1),其本身被第三区域( 3)与晶体管漏极(4)相关联。 晶体管的绝缘栅极(12)存在于源极区域(1)和第三区域(3)的第一部分(31)之间的第二区域(2)的沟道区域上。 第三区域(3)还具有远离第一部分(31)的表面相邻的第二部分(32),并且优选地具有比第二和源区域(2,1)更低的掺杂浓度。 可以是源电极的电极层(11)在第三区域(3)的所述第二部分(32)上延伸并且连接到所述第二区域(2),并且存在于该电极层(11)和 第三区域(3)的第二部分(32)具有比第二和第三区域(2,3)之间的pn结(34)更低的正向压降的肖特基结(33)。 即使在驱动电感负载时,晶体管也可以具有快速的开关速度,因为肖特基结(33)在电压过流期间抑制正向偏置p-n结(34)处的少数载流子注入。 优选地,第三区域(3)的第二部分(32)由形成用于肖特基结(33)的保护环的第二区域(2)横向界定,从而保持高的阻断电压能力。 为了进一步抑制少数载流子注入,电极层(11)优选地与第二区域(2)形成肖特基结,源极区域(1)优选地围绕着肖特基接头作为保护环延伸。