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1. 发明授权

US5548785A Interface for logic simulation using parallel bus for concurrent transfers and having fifo buffers for sending data to receiving units when ready 失效
标题翻译：使用并行总线进行并行传输的逻辑仿真接口，并具有用于在准备就绪时向接收单元发送数据的fifo缓冲区
公开(公告)号：US5548785A
公开(公告)日：1996-08-20
申请号：US91521
申请日：1993-07-14
申请人： Richard G. Fogg, Jr. , Mark D. Sweet
发明人： Richard G. Fogg, Jr. , Mark D. Sweet
IPC分类号： G06F11/25 , G06F17/50 , G06F3/00
CPC分类号： G06F17/5022
摘要： A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.
摘要翻译：公开了一种用于在逻辑仿真机和主计算机之间传送数据的逻辑仿真机的主机接口。主机接口包括在逻辑模拟机和主计算机之间提供的先进先出缓冲器，用于临时存储在逻辑模拟机和主计算机之间传输的数据，直到数据的接收器准备好接收数据。主机接口在主机和逻辑仿真机之间的通信过程中，最大限度地减少了与逻辑仿真机主机交互的延迟。

2. 发明授权

US5301302A Memory mapping and special write detection in a system and method for simulating a CPU processor 失效
标题翻译：用于模拟CPU处理器的系统中的内存映射和特殊写入检测
公开(公告)号：US5301302A
公开(公告)日：1994-04-05
申请号：US680636
申请日：1991-04-02
申请人： Joe W. Blackard , Richard G. Fogg, Jr. , Arturo M. de Nicolas
发明人： Joe W. Blackard , Richard G. Fogg, Jr. , Arturo M. de Nicolas
IPC分类号： G06F9/455
CPC分类号： G06F9/45504
摘要： The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by detecting, at the time of a store to memory, whether an instruction, data, or video is being updated. If the memory location that is being updated contains an instruction, the simulator takes additional steps to guarantee the correct execution of the modified instruction. If the simulator determines at the time of a store that the memory location being modified is data, the simulator needs to take no additional steps.
摘要翻译：本发明的系统和方法通过利用在具有不同指令集的第二处理器的第二处理系统上运行的模拟器模拟针对特定处理器的特定指令集的应用程序的控制流程。模拟器通过在对存储器的存储时检测指令，数据或视频是否被更新来减少模拟第一处理器指令的控制流程所需的翻译指令的数量。如果正在更新的存储器位置包含指令，则模拟器需要额外的步骤来保证正确执行修改的指令。如果模拟器在存储时确定要修改的存储器位置是数据，则模拟器不需要采取额外的步骤。

3. 发明授权

US5251303A System for DMA block data transfer based on linked control blocks 失效
标题翻译：基于链接控制块的DMA块数据传输系统
公开(公告)号：US5251303A
公开(公告)日：1993-10-05
申请号：US297778
申请日：1989-01-13
申请人： Richard G. Fogg, Jr. , Joseph R. Mathis , James O. Nicholson
发明人： Richard G. Fogg, Jr. , Joseph R. Mathis , James O. Nicholson
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller has an attached, dedicated memory. Data objects are stored on the heap and connected by pointers. Each data object contains DMA block transfer control parameters. A single block transfer made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

4. 发明授权

US4995056A System and method for data communications 失效
标题翻译：用于数据通信的系统和方法
公开(公告)号：US4995056A
公开(公告)日：1991-02-19
申请号：US297776
申请日：1989-01-13
申请人： Richard G. Fogg, Jr. , Joseph R. Mathis , Carl Zeitler, Jr.
发明人： Richard G. Fogg, Jr. , Joseph R. Mathis , Carl Zeitler, Jr.
IPC分类号： H04L29/08 , G06F13/42
CPC分类号： G06F13/4213
摘要： In a communications system, a sending system and a receiving system have multiple data buffers. In response to an inquiry from the sending system, the receiving system transmits information which indicates the size and number of data buffers available in the receiving system. The sending system then begins transmitting data frames, which are placed into the buffers of the receiving system. When the receiving system removes all of the data from a buffer, therefore freeing it to accept additional data, it sends a signal to the sending system indicating this fact. The sending system counts such signals, and ensures that the number of transmitted data frames does not exceed the number of frames which have been removed from the receiver's buffers by more than the number of buffers which the receiver has.

5. 发明授权

US4951195A Condition code graph analysis for simulating a CPU processor 失效
标题翻译：用于模拟CPU处理器的条件码图分析
公开(公告)号：US4951195A
公开(公告)日：1990-08-21
申请号：US151136
申请日：1988-02-01
申请人： Richard G. Fogg, Jr. , Arturo M. de Nicolas
发明人： Richard G. Fogg, Jr. , Arturo M. de Nicolas
IPC分类号： G06F9/30 , G06F9/455
CPC分类号： G06F9/45504
摘要： The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by performing a graph analysis on the application's instruction flow of control to determine which condition codes of each instruction are not needed for a subsequent instruction. Fewer translated instructions are needed if the condition codes for an instruction are not set or used subsequently.

6. 发明授权

US5129064A System and method for simulating the I/O of a processing system 失效
标题翻译：用于模拟处理系统的I / O的系统和方法
公开(公告)号：US5129064A
公开(公告)日：1992-07-07
申请号：US576081
申请日：1990-08-27
申请人： Richard G. Fogg, Jr. , Arturo M. de Nicholas , John C. O'Quin, III
发明人： Richard G. Fogg, Jr. , Arturo M. de Nicholas , John C. O'Quin, III
IPC分类号： G06F13/10
CPC分类号： G06F13/105
摘要： The system and method of this invention allows a simulated processor to receive an interrupt request from I/O devices. A simulated interrupt controller routine determines whether to post an interrupt to the simulated CPU. The simulated interrupt controller routine posts an interrupt to the simulated CPU by updating one byte, which is owned by the simulated interrupt controller, of a two byte halfword. The other byte is owned by the simulated CPU and is updated by the simulated CPU when its internal interrupt enabled state changes. Each byte of the two byte halfword is updated independently, but is loaded by the simulated CPU with only one instruction to determine if an interrupt should be acknowledged.The simulated CPU minimizes the overhead of polling for an interrupt by performing a graph analysis of the instruction flow of control to determine the locations to poll for interrupts. The simulated CPU polls for an interrupt when an instruction transfers control dynamically, once around a loop, and when an instruction changes the interrupt enabled state of the simulated CPU.
摘要翻译：本发明的系统和方法允许模拟处理器从I / O设备接收中断请求。模拟中断控制器例程确定是否向仿真的CPU发送中断。模拟中断控制器程序通过更新一个字节，由模拟中断控制器拥有一个双字节半字，将中断发送给模拟CPU。另一个字节由模拟CPU拥有，并在其内部中断使能状态更改时由仿真CPU更新。两个字节半字的每个字节都是独立更新的，但是由模拟CPU加载一个指令，以确定是否应该确认一个中断。模拟CPU通过执行控制指令流的图形分析来确定中断的轮询位置，从而最大限度地减少轮询中断的开销。仿真CPU轮询一个中断，当指令在一个循环周围动态地进行控制，当指令改变模拟CPU的中断使能状态时。

7. 发明授权

US5008816A Data processing system with multi-access memory 失效
标题翻译：具有多路访问存储器的数据处理系统
公开(公告)号：US5008816A
公开(公告)日：1991-04-16
申请号：US117715
申请日：1987-11-06
申请人： Richard G. Fogg, Jr. , John W. Irwin
发明人： Richard G. Fogg, Jr. , John W. Irwin
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G09G5/36 , G09G5/39 , G09G5/399
CPC分类号： G06F12/0284 , G09G5/36 , G09G5/363
摘要： A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included that provides write access to either only a first portion of the memory locations, or simultaneously several portions of the memory locations is designated by the control information. This invention further includes a memory system that provides several memory locations for the storage of information together with the controller having a first port and a second port. The first port provides access to the memory locations in response to a first address range and the second port provides access to the memory locations in response to several address ranges wherein at least one of the address ranges of the second port is different then the address range of the first port. Still further, the invention includes a memory system having a first group of memory locations that store information in accordance with the first address range and a second group of memory locations. The two groups of memory locations are connected to a controller that provides write access to the first group of memory locations in a response to write commands having addresses within the first address range and, simultaneously writing each write command address in the second group of memory locations.

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