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1. 发明授权

US07818488B2 Memory module with registers 有权
标题翻译：带寄存器的内存模块
公开(公告)号：US07818488B2
公开(公告)日：2010-10-19
申请号：US10975810
申请日：2004-10-27
申请人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
发明人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/28 , G11C8/00
CPC分类号： G11C5/04
摘要： Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.
摘要翻译：成对的具有减少引脚的寄存器被布置成在存储器模块的前表面和后表面上重叠。输入信号INS通过寄存器以菊花链的方式串联传输，以避免输入信号INS的发散，从而保持信号完整性。每个寄存器将输入信号INS缓冲到紧靠寄存器侧面的存储体，以减少布线面积。

2. 发明授权

US07566958B2 Multi-chip package for reducing parasitic load of pin 有权
标题翻译：用于减少引脚寄生负载的多芯片封装
公开(公告)号：US07566958B2
公开(公告)日：2009-07-28
申请号：US11589192
申请日：2006-10-30
申请人： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
发明人： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
IPC分类号： H01L23/02
CPC分类号： H01L24/49 , G11C5/00 , G11C5/06 , H01L23/50 , H01L24/48 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01006 , H01L2924/01055 , H01L2924/01075 , H01L2924/30105 , H01L2224/45099 , H01L2224/05599
摘要： Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.
摘要翻译：多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

3. 发明授权

US07219274B2 Memory module and method of testing the same 有权
标题翻译：内存模块和测试方法相同
公开(公告)号：US07219274B2
公开(公告)日：2007-05-15
申请号：US10831702
申请日：2004-04-23
申请人： Jung-Bae Lee , Hoe-Ju Chung , Byung-Se So
发明人： Jung-Bae Lee , Hoe-Ju Chung , Byung-Se So
IPC分类号： G11C29/04 , G11C29/48
CPC分类号： G11C29/14 , G11C11/401 , G11C29/1201 , G11C29/48 , G11C2029/2602
摘要： A memory module, including a plurality of semiconductor memory devices for writing and reading m-bit parallel data; and a buffer for converting n-bit serial data into the m-bit parallel data to output to the plurality of semiconductor memory devices, converting the m-bit parallel data into the n-bit serial data to output to a first external portion during a normal operation, buffering 2n-bit parallel data to output to the plurality of semiconductor memory devices, and buffering the m-bit parallel data to output to a second external portion during a test operation.
摘要翻译：一种存储器模块，包括用于写入和读取m位并行数据的多个半导体存储器件; 以及用于将n位串行数据转换成m位并行数据以输出到多个半导体存储器件的缓冲器，将m位并行数据转换成n位串行数据，以在第一外部部分输出正常操作，缓冲2n位并行数据以输出到多个半导体存储器件，以及在测试操作期间缓冲m位并行数据以输出到第二外部部分。

4. 发明申请

US20070018637A1 Apparatus and method for testing circuit characteristics by using eye mask 有权
标题翻译：使用眼罩测试电路特性的装置和方法
公开(公告)号：US20070018637A1
公开(公告)日：2007-01-25
申请号：US11490984
申请日：2006-07-21
申请人： Woo-Seop Kim , Jun-Young Park , Sung-Je Hong , Sung-Bum Cho , Byung-Se So , Hyun-Chul Kang
发明人： Woo-Seop Kim , Jun-Young Park , Sung-Je Hong , Sung-Bum Cho , Byung-Se So , Hyun-Chul Kang
IPC分类号： G01R31/28
CPC分类号： G01R31/3171 , G11C29/02 , G11C29/022 , G11C29/50012 , G11C29/56
摘要： A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.
摘要翻译：一种能够通过分析在测试装置中产生的眼罩和从半导体器件的I / O电路输出的测试信号的波形来检测半导体器件的输入/输出（I / O）电路特性的测试装置。所述测试装置包括与彼此相反相位的一个或多个时钟信号同步地生成眼罩的眼罩发生器，从眼罩发生器接收眼罩并将测试信号与眼罩相比较的误差检测器以确定半导体器件中是否发生错误;以及误差信号输出单元，其接收来自误差检测器的误差检测信号，并响应于误差检测信号产生误差信号。特别地，眼罩发生器包括正弦波发生器，其与一个或多个时钟信号同步地产生彼此相反相位的一个或多个正弦波，以及限制器电路，其接收正弦波并通过调整产生眼罩正弦波的幅度。

5. 发明授权

US07148563B2 Multi-chip package for reducing parasitic load of pin 有权
标题翻译：用于减少引脚寄生负载的多芯片封装
公开(公告)号：US07148563B2
公开(公告)日：2006-12-12
申请号：US10722159
申请日：2003-11-26
申请人： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
发明人： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
IPC分类号： H01L23/02
CPC分类号： H01L24/49 , G11C5/00 , G11C5/06 , H01L23/50 , H01L24/48 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01006 , H01L2924/01055 , H01L2924/01075 , H01L2924/30105 , H01L2224/45099 , H01L2224/05599
摘要： A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal from a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other.
摘要翻译：多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。第一半导体芯片的输入/输出焊盘直接从多芯片封装的相应引脚接收输入/输出信号。第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。

6. 发明授权

US07072201B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US07072201B2
公开(公告)日：2006-07-04
申请号：US10853353
申请日：2004-05-26
申请人： Byung-se So , Jeong-hyeon Cho , Jung-joon Lee , Jae-jun Lee
发明人： Byung-se So , Jeong-hyeon Cho , Jung-joon Lee , Jae-jun Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/10 , G11C8/06 , H05K1/144 , H05K1/181
摘要： In the memory module, a buffer is disposed on one of at least two circuit boards in the memory module. The buffer is for buffering signals for memory chips on at least two circuit boards in the memory module.
摘要翻译：在存储器模块中，缓冲器被布置在存储器模块中的至少两个电路板中的一个上。缓冲器用于缓冲存储器模块中至少两个电路板上的存储器芯片的信号。

7. 发明申请

US20060006419A1 Method of testing a memory module and hub of the memory module 失效
公开(公告)号：US20060006419A1
公开(公告)日：2006-01-12
申请号：US11118377
申请日：2005-05-02
申请人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
发明人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
IPC分类号： H01L31/109
CPC分类号： G11C29/08 , G11C5/04 , G11C2029/5602
摘要： A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.

8. 发明申请

US20050097264A1 Memory module with registers 有权
标题翻译：带寄存器的内存模块
公开(公告)号：US20050097264A1
公开(公告)日：2005-05-05
申请号：US10975810
申请日：2004-10-27
申请人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
发明人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G11C5/00 , H01L23/50
CPC分类号： G11C5/04
摘要： Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.
摘要翻译：成对的具有减少引脚的寄存器被布置成在存储器模块的前表面和后表面上重叠。输入信号INS通过寄存器以菊花链的方式串联传输，以避免输入信号INS的发散，从而保持信号完整性。每个寄存器将输入信号INS缓冲到紧靠寄存器侧面的存储体，以减少布线面积。

9. 发明申请

US20110113296A1 Method of testing a memory module and hub of the memory module 失效
公开(公告)号：US20110113296A1
公开(公告)日：2011-05-12
申请号：US12926043
申请日：2010-10-22
申请人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
发明人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
IPC分类号： G06F11/22
CPC分类号： G11C29/08 , G11C5/04 , G11C2029/5602
摘要： Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

10. 发明授权

US07615869B2 Memory module with stacked semiconductor devices 有权
标题翻译：具有堆叠半导体器件的存储器模块
公开(公告)号：US07615869B2
公开(公告)日：2009-11-10
申请号：US11266428
申请日：2005-11-04
申请人： Chang-Woo Koo , Byung-Se So , Young-Jun Park
发明人： Chang-Woo Koo , Byung-Se So , Young-Jun Park
IPC分类号： H01L23/48 , B21F41/00 , H01G4/06
CPC分类号： H01L25/105 , B82Y10/00 , G11C5/02 , G11C5/04 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/3011 , H01L2924/3511 , H05K1/0231 , H01L2924/00012
摘要： Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).
摘要翻译：描述了其中集成电路封装的堆叠布置包括虚拟衬底的虚拟衬底，该虚拟衬底包括连接到第一和/或第二电源电压的嵌入式离散或分布式电容器，或者连接到一个或多个时钟，控制，地址和 /或数据信号。

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