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1. 发明申请

US20070018637A1 Apparatus and method for testing circuit characteristics by using eye mask 有权
标题翻译：使用眼罩测试电路特性的装置和方法
公开(公告)号：US20070018637A1
公开(公告)日：2007-01-25
申请号：US11490984
申请日：2006-07-21
申请人： Woo-Seop Kim , Jun-Young Park , Sung-Je Hong , Sung-Bum Cho , Byung-Se So , Hyun-Chul Kang
发明人： Woo-Seop Kim , Jun-Young Park , Sung-Je Hong , Sung-Bum Cho , Byung-Se So , Hyun-Chul Kang
IPC分类号： G01R31/28
CPC分类号： G01R31/3171 , G11C29/02 , G11C29/022 , G11C29/50012 , G11C29/56
摘要： A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.
摘要翻译：一种能够通过分析在测试装置中产生的眼罩和从半导体器件的I / O电路输出的测试信号的波形来检测半导体器件的输入/输出（I / O）电路特性的测试装置。所述测试装置包括与彼此相反相位的一个或多个时钟信号同步地生成眼罩的眼罩发生器，从眼罩发生器接收眼罩并将测试信号与眼罩相比较的误差检测器以确定半导体器件中是否发生错误;以及误差信号输出单元，其接收来自误差检测器的误差检测信号，并响应于误差检测信号产生误差信号。特别地，眼罩发生器包括正弦波发生器，其与一个或多个时钟信号同步地产生彼此相反相位的一个或多个正弦波，以及限制器电路，其接收正弦波并通过调整产生眼罩正弦波的幅度。

2. 发明授权

US07656181B2 Apparatus and method for testing circuit characteristics by using eye mask 有权
标题翻译：使用眼罩测试电路特性的装置和方法
公开(公告)号：US07656181B2
公开(公告)日：2010-02-02
申请号：US11490984
申请日：2006-07-21
申请人： Woo-Seop Kim , Jun-Young Park , Sung-Je Hong , Sung-Bum Cho , Byung-Se So , Hyun-Chul Kang
发明人： Woo-Seop Kim , Jun-Young Park , Sung-Je Hong , Sung-Bum Cho , Byung-Se So , Hyun-Chul Kang
IPC分类号： G01R31/26
CPC分类号： G01R31/3171 , G11C29/02 , G11C29/022 , G11C29/50012 , G11C29/56
摘要： A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.
摘要翻译：一种能够通过分析在测试装置中产生的眼罩和从半导体器件的I / O电路输出的测试信号的波形来检测半导体器件的输入/输出（I / O）电路特性的测试装置。所述测试装置包括与彼此相反相位的一个或多个时钟信号同步地生成眼罩的眼罩发生器，从眼罩发生器接收眼罩并将测试信号与眼罩相比较的误差检测器以确定半导体器件中是否发生错误;以及误差信号输出单元，其接收来自误差检测器的误差检测信号，并响应于误差检测信号产生误差信号。特别地，眼罩发生器包括正弦波发生器，其与一个或多个时钟信号同步地产生彼此相反相位的一个或多个正弦波，以及限制器电路，其接收正弦波并通过调整产生眼罩正弦波的幅度。

3. 发明申请

US20050097410A1 Memory device and input signal control method of a memory device 失效
标题翻译：存储器件的存储器件和输入信号控制方法
公开(公告)号：US20050097410A1
公开(公告)日：2005-05-05
申请号：US10975006
申请日：2004-10-28
申请人： Sang-Gyu Lim , Sung-Bum Cho
发明人： Sang-Gyu Lim , Sung-Bum Cho
IPC分类号： G11C7/10 , G11C29/48 , G11C29/00
CPC分类号： G11C29/1201 , G11C29/48
摘要： A memory device and a method of controlling an input signal of the memory device. In the method of controlling an input signal according to test modes, it is determined whether the input signal is in a first test mode or a second test mode. If the memory device is in the first test mode, in response to a control signal, an input signal is received through input pins. In response to a mode signal, the input signal is separated into data and an address. The separated data and address is applied to the core of a memory device. If the memory device is in the second test mode, an input signal is received through input pins and inverting input pins. In response to a mode signal, an address is separated from the input signal received through the input pins and the data is separated from the input signal received through the inverting input pins. The separated data and address are applied to the core of a memory device.
摘要翻译：存储装置和控制存储装置的输入信号的方法。在根据测试模式控制输入信号的方法中，确定输入信号是处于第一测试模式还是第二测试模式。如果存储器件处于第一测试模式，则响应于控制信号，通过输入引脚接收输入信号。响应于模式信号，输入信号被分成数据和地址。分离的数据和地址被应用于存储器件的核心。如果存储器件处于第二测试模式，则通过输入引脚和反相输入引脚接收输入信号。响应于模式信号，地址与通过输入引脚接收的输入信号分离，数据与通过反相输入引脚接收的输入信号分离。分离的数据和地址被应用于存储器件的核心。

4. 发明授权

US5285664A Automatic washing machines 失效
标题翻译：自动洗衣机
公开(公告)号：US5285664A
公开(公告)日：1994-02-15
申请号：US15635
申请日：1993-02-09
申请人： Suk-Kyu Chang , Sung-Bum Cho , Yong-Bum Shim
发明人： Suk-Kyu Chang , Sung-Bum Cho , Yong-Bum Shim
IPC分类号： D06F39/08 , D06F39/10 , D06F38/09
CPC分类号： D06F39/083
摘要： An automatic washing machine having an improved structure. The sprinkling member for repeatedly sprinkling the washing water into the dehydrating tub comprises a removable washing tub lid, an adapter for permitting the washing water to be fed therethrough and a guide member forming, in cooperation with the washing tub lid, a sprinkling nozzle through which the washing water is sprinkled into the dehydrating tub. The lint filter filters off lints generated in the washing cycle and permits the filtered lints to be automatically removed therefrom so as to be drained off the washing machine along with the drained water. The circulation pump circulates the washing water and is connected to the washing tub and the sprinkling member in such a manner that it permits the washing water in the washing cycle to be drawn up to the sprinkling member through the lint filter and also permits the used washing water in the draining cycle to downwardly pass through the filter so as to be drained off the washing machine. This washing machine thus causes the detergent particles to be finely ground by the rotation of the pump impeller so as to be completely dissolved in the washing water and permits the lints generated in the washing to be filtered off and in turn automatically discharged therefrom.
摘要翻译：一种具有改进结构的自动洗衣机。用于将洗涤水重复地喷洒到脱水槽中的喷洒构件包括可移除的洗涤桶盖，用于允许洗涤水被供给的适配器，以及与洗涤桶盖一起形成的喷洒喷嘴，引导构件将洗涤水喷入脱水桶中。棉绒过滤器过滤掉在洗涤循环中产生的棉绒，并且允许自动从其中除去过滤的棉绒，以便与排出的水一起从洗衣机中排出。循环泵循环洗涤水，并且以这样的方式连接到洗涤桶和喷洒构件，使得洗涤循环中的洗涤水通过棉绒过滤器被吸引到喷洒构件，并且还允许使用洗涤排水循环中的水向下通过过滤器，以便从洗衣机中排出。因此，这种洗衣机通过泵叶轮的旋转使洗涤剂颗粒细磨，以便完全溶解在洗涤水中，并且允许洗涤中产生的棉绒被过滤掉，从而自动排出。

5. 发明授权

US07574636B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07574636B2
公开(公告)日：2009-08-11
申请号：US11561023
申请日：2006-11-17
申请人： Hi-Choon Lee , Sung-Bum Cho
发明人： Hi-Choon Lee , Sung-Bum Cho
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/1201 , G11C2029/2602
摘要： The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation, and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.
摘要翻译：本发明提供一种包括存储单元阵列的半导体存储器件，该存储单元阵列包括多个存储区域，地址解码部分，用于解码从外部部分施加的地址，用于在测试读取操作期间同时选择所有多个存储器区域; 数据IO控制部分，用于在测试写入操作期间接收测试图案数据并将测试图案数据写入到多个存储器区域中的每一个，并且从多个存储区域中的一个读取测试图案数据，并在测试读取操作，用于从外部部分接收测试图案数据并在测试写入操作期间将测试图案数据应用于数据IO控制部分的数据IO部分，以及从数据IO控制部分输出的测试图案数据并响应于外部条件将测试图形数据作为测试状态数据输出到外部部分在测试读取操作期间放置控制信号，以及测试控制信号生成部分，用于比较从多个存储区域读取的测试图形数据，以产生输出控制信号，用于有条件地输出测试模式数据作为测试状态数据读操作。

6. 发明授权

US5659549A Memory test system having a pattern generator for a multi-bit test 失效
标题翻译：具有用于多位测试的模式发生器的存储器测试系统
公开(公告)号：US5659549A
公开(公告)日：1997-08-19
申请号：US702929
申请日：1996-08-26
申请人： Sang-Chul Oh , Sung-Bum Cho
发明人： Sang-Chul Oh , Sung-Bum Cho
IPC分类号： G01R31/28 , G11C29/00 , G11C29/56 , G06F11/00
CPC分类号： G11C29/56
摘要： A semiconductor memory testing methods and apparatus are arranged to accommodate a multi-bit mode of testing operation in which the memory under test itself includes internal peripheral circuits for comparing the contents of memory cells for multi-bit testing, and outputting a single-bit indicative of whether or not said multiple cells have the same state. The present invention includes methods and apparatus for determining the polarity of a memory cell under test, and taking that polarity into account informing expected data to be compared to the output of the memory under test.
摘要翻译：半导体存储器测试方法和装置被设置为适应测试操作的多位模式，其中被测存储器本身包括用于比较用于多位测试的存储器单元的内容的内部外围电路，并且输出单位指示是否所述多个单元是否具有相同的状态。本发明包括用于确定被测试存储器单元的极性的方法和装置，并将该极性考虑在内，以便将预期数据与被测存储器的输出进行比较。

7. 发明申请

US20080259695A1 Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices 审中-公开
标题翻译：具有解复用器的半导体存储器件和测试这种半导体存储器件的相关方法
公开(公告)号：US20080259695A1
公开(公告)日：2008-10-23
申请号：US12044094
申请日：2008-03-07
申请人： Sung-Bum Cho
发明人： Sung-Bum Cho
IPC分类号： G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/109 , G11C29/1201 , G11C29/48 , G11C29/56 , G11C2029/5602
摘要： A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input port that is configured to receive a control signal that identifies a type of signal that is input to the first input port. Related methods of testing semiconductor memory devices are also provided.
摘要翻译：半导体存储器件包括存储单元阵列和解复用器，其具有被配置为接收地址信号和数据信号的第一输入端口和被配置为接收标识信号类型的控制信号的第二输入端口这是输入到第一个输入端口。还提供了相关测试半导体存储器件的方法。

8. 发明申请

US20080046788A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080046788A1
公开(公告)日：2008-02-21
申请号：US11561023
申请日：2006-11-17
申请人： Hi-Choon Lee , Sung-Bum Cho
发明人： Hi-Choon Lee , Sung-Bum Cho
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/1201 , G11C2029/2602
摘要： The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation, and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.
摘要翻译：本发明提供一种包括存储单元阵列的半导体存储器件，该存储单元阵列包括多个存储区域，地址解码部分，用于解码从外部部分施加的地址，用于在测试读取操作期间同时选择所有多个存储器区域; 数据IO控制部分，用于在测试写入操作期间接收测试图案数据并将测试图案数据写入到多个存储器区域中的每一个，并且从多个存储区域中的一个读取测试图案数据，并在测试读取操作，用于从外部部分接收测试图案数据并在测试写入操作期间将测试图案数据应用于数据IO控制部分的数据IO部分，以及从数据IO控制部分输出的测试图案数据并响应于外部条件将测试图形数据作为测试状态数据输出到外部部分在测试读取操作期间放置控制信号，以及测试控制信号生成部分，用于比较从多个存储区域读取的测试图形数据，以产生输出控制信号，用于有条件地输出测试模式数据作为测试状态数据读操作。

9. 发明授权

US07281179B2 Memory device and input signal control method of a memory device 失效
标题翻译：存储器件的存储器件和输入信号控制方法
公开(公告)号：US07281179B2
公开(公告)日：2007-10-09
申请号：US10975006
申请日：2004-10-28
申请人： Sang-Gyu Lim , Sung-Bum Cho
发明人： Sang-Gyu Lim , Sung-Bum Cho
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/1201 , G11C29/48
摘要： A memory device and a method of controlling an input signal of the memory device. In the method of controlling an input signal according to test modes, it is determined whether the input signal is in a first test mode or a second test mode. If the memory device is in the first test mode, in response to a control signal, an input signal is received through input pins. In response to a mode signal, the input signal is separated into data and an address. The separated data and address is applied to the core of a memory device. If the memory device is in the second test mode, an input signal is received through input pins and inverting input pins. In response to a mode signal, an address is separated from the input signal received through the input pins and the data is separated from the input signal received through the inverting input pins. The separated data and address are applied to the core of a memory device.
摘要翻译：存储装置和控制存储装置的输入信号的方法。在根据测试模式控制输入信号的方法中，确定输入信号是处于第一测试模式还是第二测试模式。如果存储器件处于第一测试模式，则响应于控制信号，通过输入引脚接收输入信号。响应于模式信号，输入信号被分成数据和地址。分离的数据和地址被应用于存储器件的核心。如果存储器件处于第二测试模式，则通过输入引脚和反相输入引脚接收输入信号。响应于模式信号，地址与通过输入引脚接收的输入信号分离，数据与通过反相输入引脚接收的输入信号分离。分离的数据和地址被应用于存储器件的核心。

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