专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07242338B2 Differential digital-to-analog converter 失效
标题翻译：差分数模转换器
公开(公告)号：US07242338B2
公开(公告)日：2007-07-10
申请号：US11195301
申请日：2005-08-02
申请人： Xuewen Jiang , Bobby B. Nikjou , Waleed Khalil , Syed R. Naqvi
发明人： Xuewen Jiang , Bobby B. Nikjou , Waleed Khalil , Syed R. Naqvi
IPC分类号： H03M1/78
CPC分类号： H03M1/0682 , H03M1/687 , H03M1/765 , H03M1/785
摘要： Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.
摘要翻译：简而言之，根据本发明的一个实施例，在收发器的发射机路径中使用的差分数模转换器利用差分R2R架构。这种差分数模转换器可以用于具有较高面积效率的更高速度，更低功率和更高分辨率的应用中，例如在WCDMA应用中。

2. 发明授权

US5347558A Input frequency converter to increase input frequency range of a synchronous delay line 失效
标题翻译：输入变频器增加同步延迟线的输入频率范围
公开(公告)号：US5347558A
公开(公告)日：1994-09-13
申请号：US139196
申请日：1993-10-20
申请人： Bobby B. Nikjou
发明人： Bobby B. Nikjou
IPC分类号： H03K5/00 , H03L1/00 , H03L7/081 , H03K21/00
CPC分类号： H03L7/0812 , H03K5/00006 , H03L1/00
摘要： A front end scalar to a frequency multiplier such as a synchronous delay line (SDL) allows the SDL to operate at a single clock frequency for all multiplier coefficients and input frequencies and provides for maximum SDL design margins. A frequency multiplier of this type relies upon a feedback voltage to maintain a desired output clock frequency. So long as the input clock frequency is within predetermined limits, the feedback voltage will maintain the output frequency at a desired frequency for which the SDL has been optimized. As the input frequency approaches the upper or lower limit for which an SDL basic building block has been optimized, it may become impossible for an SDL to provide frequency lock since control voltage is already below or above V.sub.cc /2 due to a lower or a higher input frequency. The invention operates to ensure that the input frequency to the SDL is always close to the frequency for which the SDL has been optimized by changing the input frequency to a frequency which is at or near the frequency for which a SDL has been optimized and thereby eliminate the input frequency dependency of the SDL.
摘要翻译：诸如同步延迟线（SDL）的倍增器的前端标量允许SDL以所有乘数系数和输入频率的单个时钟频率工作，并提供最大的SDL设计余量。这种类型的倍频器依赖于反馈电压来维持期望的输出时钟频率。只要输入时钟频率在预定的范围内，反馈电压将使输出频率保持在SDL已被优化的期望频率。当输入频率接近已经优化了SDL基本构建块的上限或下限时，SDL可能不可能提供频率锁定，因为由于较低或较高的控制电压已经低于或高于Vcc / 2 输入频率。本发明用于确保通过将输入频率改变为SDL已被优化的频率处于或接近SDL的频率从而消除SDL的输入频率总是接近SDL已被优化的频率，从而消除 SDL的输入频率依赖性。

3. 发明授权

US06924761B2 Differential digital-to-analog converter 失效
标题翻译：差分数模转换器
公开(公告)号：US06924761B2
公开(公告)日：2005-08-02
申请号：US10601038
申请日：2003-06-19
申请人： Xuewen Jiang , Bobby B. Nikjou , Waleed Khalil , Syed R. Naqvi
发明人： Xuewen Jiang , Bobby B. Nikjou , Waleed Khalil , Syed R. Naqvi
IPC分类号： H03M1/06 , H03M1/68 , H03M1/76 , H03M1/78
CPC分类号： H03M1/0682 , H03M1/687 , H03M1/765 , H03M1/785
摘要： Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.
摘要翻译：简而言之，根据本发明的一个实施例，在收发器的发射机路径中使用的差分数模转换器利用差分R2R架构。这种差分数模转换器可以用于具有较高面积效率的更高速度，更低功率和更高分辨率的应用中，例如在WCDMA应用中。

4. 发明授权

US5638542A Low power non-overlap two phase complementary clock unit using synchronous delay line 失效
标题翻译：低功耗非重叠两相互补时钟单元采用同步延时线
公开(公告)号：US5638542A
公开(公告)日：1997-06-10
申请号：US643406
申请日：1996-05-06
申请人： Bobby B. Nikjou
发明人： Bobby B. Nikjou
IPC分类号： G06F1/06 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/06 , G06F1/3203 , Y02B60/1217 , Y02B60/1282
摘要： A clock generator which utilizes a SDL, power management circuitry, phase drivers and non-overlap logic all integrated on a single chip to output a set of non-overlapped, complementary clock phases for each processor and for on board peripherals. The present invention also has application for use with multiple discrete processors used on an application or system validation board where one or more of the processors may run at different clock speeds from the others or be stopped. The integrated non-overlap logic reduces the clock skewing among various component on the application board, thus, increasing the overall performance of the system. The present invention is specifically directed to clock generation circuitry including a circuit which receives clock phases generated by a SDL, or from a set of frequency dividers and produces non-overlapped clock phases for each on-board processor and for the on-board peripherals.
摘要翻译：时钟发生器利用SDL，电源管理电路，相位驱动器和非重叠逻辑，它们都集成在单个芯片上，为每个处理器和板上外设输出一组非重叠，互补的时钟相位。本发明还具有用于在应用或系统验证板上使用的多个分立处理器的应用，其中一个或多个处理器可以以与其他时钟不同的时钟速度运行或停止。集成的非重叠逻辑减少了应用板上各种组件之间的时钟偏移，从而提高了系统的整体性能。本发明特别涉及时钟生成电路，其包括接收由SDL或一组分频器产生的时钟相位并且为每个板载处理器和板上外设产生非重叠时钟相位的电路的电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式