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1. 发明授权

US08010510B1 Method and system for tokenized stream compression 有权
标题翻译：令牌化流压缩的方法和系统
公开(公告)号：US08010510B1
公开(公告)日：2011-08-30
申请号：US12167116
申请日：2008-07-02
申请人： Binh Vo , Gurmeet Singii Manku
发明人： Binh Vo , Gurmeet Singii Manku
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F7/22 , G06F17/30516 , G06F17/30985 , H03M7/40 , H03M7/46
摘要： A tokenized stream including n tokens, each token including two or more portions, is received and a first sort order based on a sort of a set of the first portions of the n tokens is determined. The first sort order is applied to reorder a set of the second portions of the n tokens. The above steps are repeated to determine a sort order based on a set of portions of the n tokens and to apply the sort order to another set of portions of the n tokens column until a cth set of portions been reordered by a (c−1)th sort order. The variable c is a desired number of sets to be sorted. The variables c and n are whole numbers and the n tokens are dispersed during reordering.
摘要翻译：接收包括n个令牌的令牌化流，每个令牌包括两个或多个部分，并且确定基于n个令牌的第一部分的集合的排序的第一排序顺序。第一种排序顺序被应用于重新排列n个令牌的一组第二部分。重复上述步骤以基于n个令牌的一组部分来确定排序顺序，并将排序顺序应用于n个令牌列的另一组部分，直到第c个部分集合被（c-1）重新排序）排序顺序。变量c是要排序的所需数量的集合。变量c和n是整数，n个令牌在排序过程中分散。

2. 发明授权

US07685485B2 Functional failure analysis techniques for programmable integrated circuits 失效
标题翻译：用于可编程集成电路的功能故障分析技术
公开(公告)号：US07685485B2
公开(公告)日：2010-03-23
申请号：US10698739
申请日：2003-10-30
申请人： Binh Vo , Wan-Pin Hung , David Huang , Peter Boyle , Qi Richard Chen , Kaiyu Ren , Adam J. Wright , John DiCosola , Laiq Chughtai , Seng Yew Lim
发明人： Binh Vo , Wan-Pin Hung , David Huang , Peter Boyle , Qi Richard Chen , Kaiyu Ren , Adam J. Wright , John DiCosola , Laiq Chughtai , Seng Yew Lim
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31705 , G01R31/318516
摘要： Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.
摘要翻译：提供了用于隔离可编程电路上的故障路由资源的技术。失败的测试模式和测试日志被馈送到统计失效隔离（SFI）工具。 SFI工具提取测试模式的失败路径。对与故障路径相关的互连资源进行统计分析。然后对路径上的资源进行计算，以创建资源直方图。然后将这些资源馈送到自适应故障隔离（AFI）工具中，以自动生成验证模式。测试人员使用验证模式来隔离故障的互连资源。

3. 发明授权

US07571412B1 Method and system for semiconductor device characterization pattern generation and analysis 失效
标题翻译：用于半导体器件表征模式生成和分析的方法和系统
公开(公告)号：US07571412B1
公开(公告)日：2009-08-04
申请号：US11377714
申请日：2006-03-15
申请人： Hung Hing Anthony Pang , Binh Vo , Souvik Ghosh
发明人： Hung Hing Anthony Pang , Binh Vo , Souvik Ghosh
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G01R31/31727 , G01R31/31813 , G01R31/3183 , G06F2217/62
摘要： A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.
摘要翻译：提供了一种用于产生集成电路（IC）的自动设计表征模式的方法。该方法包括从包含IC的路由的设备描述的文件中选择路由方案。在一个实施例中，路由方案可以是锁相环，时钟树，延迟元件或输入输出块。标识路由方案的资源类型，并在资源之间的约束内定义路径。一旦定义了一个路径，就可以通过从路径的末尾到路径的开头的路径重新定义约束中的路径来定义备用路径。然后构建替代路径，替代路径共享之前定义的路径的一部分。还提供了提供该方法功能的计算系统。

4. 发明授权

US07024327B1 Techniques for automatically generating tests for programmable circuits 失效
标题翻译：自动生成可编程电路测试的技术
公开(公告)号：US07024327B1
公开(公告)日：2006-04-04
申请号：US10323506
申请日：2002-12-18
申请人： Jayabrata Ghosh Dastidar , Adam Wright , Hung Hing Anthony Pang , Binh Vo , Ajay Nagarandal , Paul J. Tracy , Michael Harms
发明人： Jayabrata Ghosh Dastidar , Adam Wright , Hung Hing Anthony Pang , Binh Vo , Ajay Nagarandal , Paul J. Tracy , Michael Harms
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G01R31/318314 , G01R31/318307
摘要： Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.
摘要翻译：可编程电路具有连接可编程电路元件的可编程互连结构。对可编程电路元件和可编程电路的互连可以自动生成测试图案。连接图表示可编程互连并作为节点。生成测试路线，连接可控电路上的控制点和观测点之间的连接图中的节点。路由被分组成可以在一个测试周期中测试的配置模式。然后将测试向量应用于路由以确定互连和电路功能是否可操作。本发明的系统和方法自动创建可编程电路的测试模式，以减少工程师的时间。本发明还通过增加在每个配置模式中测试的互连和电路元件的数量来减少测试时间和资源。

5. 发明申请

US20060031673A1 Method and system for detecting infection of an operating system 有权
公开(公告)号：US20060031673A1
公开(公告)日：2006-02-09
申请号：US10997768
申请日：2004-11-23
申请人： Douglas Beck , Aaron Johnson , Roussi Roussev , Chad Verbowski , Binh Vo , Yi-Min Wang
发明人： Douglas Beck , Aaron Johnson , Roussi Roussev , Chad Verbowski , Binh Vo , Yi-Min Wang
IPC分类号： H04L9/00
CPC分类号： G06F21/565
摘要： A method and system for detecting that a software system has been infected by software that attempts to hide properties related to the software system is provided. A detection system identifies that a suspect operating system has been infected by malware by comparing properties related to the suspect operating system as reported by the suspect operating system to properties as reported by another operating system that is assumed to be clean. The detection system compares the reported properties to the actual properties to identify any significant differences. A significant difference, such as the presence of an actual file not reported by the suspect operating system, may indicate that the suspect storage device is infected.

6. 发明申请

US20050044294A1 Method and apparatus for window matching in delta compressors 有权
标题翻译：三角压缩机窗口匹配的方法和装置
公开(公告)号：US20050044294A1
公开(公告)日：2005-02-24
申请号：US10894424
申请日：2004-07-19
申请人： Binh Vo , Kiem-Phong Vo
发明人： Binh Vo , Kiem-Phong Vo
IPC分类号： G06F17/00 , H03M7/30 , G06F11/34 , G06F3/00
CPC分类号： H03M7/30 , Y10S707/99931 , Y10S707/99935 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： The present invention provides efficient target file window matching within the source file for delta compressors.
摘要翻译：本发明在三角洲压缩机的源文件内提供有效的目标文件窗口匹配。

7. 发明授权

US08516322B1 Automatic test pattern generation system for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的自动测试图生成系统
公开(公告)号：US08516322B1
公开(公告)日：2013-08-20
申请号：US12568136
申请日：2009-09-28
申请人： Jayabrata Ghosh Dastidar , Alok Shreekant Doshi , Binh Vo , Kalyana Ravindra Kantipudi , Sergey Timokhin
发明人： Jayabrata Ghosh Dastidar , Alok Shreekant Doshi , Binh Vo , Kalyana Ravindra Kantipudi , Sergey Timokhin
IPC分类号： G01R31/3183 , G01R31/40
CPC分类号： G01R31/3183
摘要： A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.
摘要翻译：可编程集成电路可以包含多个逻辑块。计算设备可用于运行自动化工具，处理可编程集成电路的设计以执行相应的电路测试。翻译工具可以将可编程集成电路上的电路的晶体管级描述转换成门级描述。块级测试配置数据生成工具可以生成块级测试配置数据文件。测试配置数据文件可以用作产生块级测试向量的自动测试模式生成工具的约束。全芯片传播工具可以使用块级测试向量，块级测试配置数据文件和全芯片约束来产生相应的全芯片测试配置数据和用于测试集成电路的全芯片测试向量。翻译工具可将配置数据和测试向量转换为测试文件。

8. 发明申请

US20080040375A1 METHOD AND APPARATUS FOR WINDOWING IN ENTROPY ENCODING 有权
标题翻译： WINDOWING IN ENTROPY编码的方法和装置
公开(公告)号：US20080040375A1
公开(公告)日：2008-02-14
申请号：US11871391
申请日：2007-10-12
申请人： Binh Vo , Kiem-Phong Vo
发明人： Binh Vo , Kiem-Phong Vo
IPC分类号： G06F17/30
CPC分类号： H03M7/30 , Y10S707/99931 , Y10S707/99935 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： The present invention provides efficient window partitioning algorithms for entropy-encoding. The present invention enhances compression performance of entropy encoding based on the approach of modeling a dataset with the frequencies of its n-grams. The present invention may then employ approximation algorithms to compute good partitions in time O(s*log s) and O(s) respectively, for any data segment S with length s.
摘要翻译：本发明提供了用于熵编码的有效的窗口分割算法。本发明基于用其n-gram的频率建模数据集的方法来增强熵编码的压缩性能。然后，本发明可以使用近似算法来计算具有长度s的任何数据段S的时间O（s * log s）和O（s）的良好分区。

9. 发明申请

US20050055367A1 Method and apparatus for windowing in entropy encoding 失效
标题翻译：用于在熵编码中加窗的方法和装置
公开(公告)号：US20050055367A1
公开(公告)日：2005-03-10
申请号：US10894421
申请日：2004-07-19
申请人： Binh Vo , Kiem-Phong Vo
发明人： Binh Vo , Kiem-Phong Vo
IPC分类号： G06F17/00 , H03M7/30
CPC分类号： H03M7/30 , Y10S707/99931 , Y10S707/99935 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： The present invention provides efficient window partitioning algorithms for entropy-encoding. The present invention enhances compression performance of entropy encoding based on the approach of modeling a dataset with the frequencies of its n-grams. The present invention may then employ approximation algorithms to compute good partitions in time O(s*log s) and O(s) respectively, for any data segment S with length s.
摘要翻译：本发明提供了用于熵编码的有效的窗口分割算法。本发明基于用其n-gram的频率建模数据集的方法来增强熵编码的压缩性能。然后，本发明可以使用近似算法来计算具有长度s的任何数据段S的时间O（s * log s）和O（s）的良好分区。

10. 发明授权

US06171463B2 Electrophoresis method and apparatus for separating bio-organic molecules 有权
标题翻译：用于分离生物有机分子的电泳方法和设备
公开(公告)号：US06171463B2
公开(公告)日：2001-01-09
申请号：US09301080
申请日：1999-04-28
申请人： Barton G. Selby , Johan Goudberg , Binh Vo , David Clark , Thomas Sch{grave over (e)}fer , Munechika Sakabe
发明人： Barton G. Selby , Johan Goudberg , Binh Vo , David Clark , Thomas Sch{grave over (e)}fer , Munechika Sakabe
IPC分类号： G01N2726
CPC分类号： G01N27/44743
摘要： The present invention relates to the electrophoretic separation of bio-organic molecules using a slab gel electrophoresis apparatus having a pair of spaced, confronting plates defining a multi-lane separation zone adapted to hold a separation medium and an upper loading zone. In one aspect of the invention, at least one of the plates is shaped to provide an expanded loading zone. The plate-to-plate distance within the expanded loading zone is greater than the plate-to-plate width within the separation zone. In another aspect of the invention, a comb is provided with each tooth having a gradual taper beginning at a support member and extending along most of the tooth's longitudinal axis, and a sharp taper beginning immediately beyond the gradual taper and extending to the end of the tooth. In a related aspect of the invention, a method is provided wherein a comb is inserted into the loading zone so that the teeth penetrate an upper portion of the separation medium, thereby forming a series of fluid-tight, elongate sample-loading apertures of substantially rectangular cross-section having a plate-to-plate width greater than that of the inter-plate distance in the separation zone. Methods of separating biomolecule analytes for optimized resolution and increased base reads are also disclosed.
摘要翻译：本发明涉及使用板式凝胶电泳装置的生物有机分子的电泳分离，所述板式凝胶电泳装置具有限定适于保持分离介质和上装载区的多通道分离区的一对间隔开的面对板。在本发明的一个方面中，至少一个板被成形为提供一个膨胀的加载区。扩展加载区内的板间距离大于分离区内的板对板宽度。在本发明的另一方面，梳子具有每个齿具有从支撑构件开始并且沿着该齿的纵向轴线的大部分延伸的渐变锥形的逐渐渐缩锥形，以及紧接着逐渐变细并且延伸至齿。在本发明的相关方面，提供了一种方法，其中将梳子插入装载区域中，使得齿穿透分离介质的上部，由此形成一系列流体密封的细长的样品加载孔，其基本上矩形横截面的板对板宽度大于分离区中的板间距离。还公开了用于优化分辨率和增加的碱基读数分离生物分子分析物的方法。

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