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1. 发明申请

US20070241458A1 Metal / metal nitride barrier layer for semiconductor device applications 失效
标题翻译：用于半导体器件应用的金属/金属氮化物阻挡层
公开(公告)号：US20070241458A1
公开(公告)日：2007-10-18
申请号：US11809153
申请日：2007-05-30
申请人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
发明人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
IPC分类号： H01L23/48
CPC分类号： H01L21/02183 , C23C14/024 , C23C14/046 , C23C14/0641 , C23C14/165 , C23C14/541 , C23C14/5806 , H01L21/022 , H01L21/02266 , H01L21/02271 , H01L21/02362 , H01L21/2855 , H01L21/318 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal/metal nitride barrier layer for semiconductor device applications. The barrier layer is particularly useful in contact vias where high conductivity of the via is important, and a lower resistivity barrier layer provides improved overall via conductivity.
摘要翻译：用于半导体器件应用的金属/金属氮化物阻挡层。阻挡层在通孔的高导电性很重要的接触孔中特别有用，并且较低电阻率的阻挡层提供改进的整体通孔导电性。

2. 发明申请

US20060223286A1 ATOMIC LAYER DEPOSITION APPARATUS 有权
标题翻译：原子层沉积装置
公开(公告)号：US20060223286A1
公开(公告)日：2006-10-05
申请号：US11423535
申请日：2006-06-12
申请人： Barry Chin , Alfred Mak , Lawrence Lei , Ming Xi , Hua Chung , Ken Lai , Jeong Byun
发明人： Barry Chin , Alfred Mak , Lawrence Lei , Ming Xi , Hua Chung , Ken Lai , Jeong Byun
IPC分类号： C23C16/00 , H01L21/20
CPC分类号： C23C16/45544 , C23C16/45525 , C23C16/45548 , C23C16/45551 , C23C16/4583
摘要： A method and apparatus for atomic layer deposition (ALD) is described. The apparatus comprises a deposition chamber and a wafer support. The deposition chamber is divided into two or more deposition regions that are integrally connected one to another. The wafer support is movable between the two or more interconnected deposition regions within the deposition chamber.
摘要翻译：描述了用于原子层沉积（ALD）的方法和装置。该装置包括沉积室和晶片支架。沉积室被分成两个或更多个彼此一体地连接的沉积区域。晶片支撑件可在沉积室内的两个或更多互连的沉积区域之间移动。

3. 发明申请

US20050085068A1 Method of depositing a metal seed layer on semiconductor substrates 失效
标题翻译：在半导体衬底上沉积金属种子层的方法
公开(公告)号：US20050085068A1
公开(公告)日：2005-04-21
申请号：US10981319
申请日：2004-11-03
申请人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
发明人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
IPC分类号： H01L21/285 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.
摘要翻译：我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被腐蚀掉或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合，受离子影响的表面不会以对器件性能或寿命有害的量溅射。随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

4. 发明授权

US06566259B1 Integrated deposition process for copper metallization 有权
标题翻译：铜金属化的集成沉积工艺
公开(公告)号：US06566259B1
公开(公告)日：2003-05-20
申请号：US09710383
申请日：2000-11-09
申请人： Peijun Ding , Imran Hashim , Barry Chin , Bingxi Sun
发明人： Peijun Ding , Imran Hashim , Barry Chin , Bingxi Sun
IPC分类号： H01L214763
CPC分类号： H01L21/76876 , C23C14/0641 , C23C14/165 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L21/76882
摘要： Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.
摘要翻译：金属化处理序列被提供用于形成可靠的互连，包括线，通孔和触点。首先在图案化衬底上形成初始阻挡层，例如Ta或TaN，然后使用高密度等离子体PVD技术形成晶种层。然后使用1）电镀，2）PVD回流，3）CVD，然后PVD回流或4）CVD来填充该结构。

5. 发明授权

US06458251B1 Pressure modulation method to obtain improved step coverage of seed layer 失效
标题翻译：压力调制方法获得改善种子层的覆盖面
公开(公告)号：US06458251B1
公开(公告)日：2002-10-01
申请号：US09440679
申请日：1999-11-16
申请人： Arvind Sundarrajan , Darryl Angelo , Peijun Ding , Barry Chin , Imran Hasim
发明人： Arvind Sundarrajan , Darryl Angelo , Peijun Ding , Barry Chin , Imran Hasim
IPC分类号： C23C1432
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/3492 , C23C14/358 , H01J37/32082 , H01J37/3402 , H01J2237/3327 , H01L21/2855 , H01L21/76873 , H01L21/76877
摘要： A multi-step process for the deposition of a material into high aspect ratio features on a substrate surface is provided. The process involves depositing a material on the substrate at a first pressure for a first period of time and then depositing the material on the substrate at a second pressure for a second period of time. Modulation of the pressure influences the ionization and trajectory of the particles, which are ionized in a plasma environment. The method of the invention in one aspect allows for optimum deposition at the bottom of a high aspect ratio feature during a high pressure step and increased deposition on the sidewalls of the feature during at least a low pressure step.
摘要翻译：提供了用于将材料沉积到衬底表面上的高纵横比特征的多步骤过程。该方法包括在第一压力下在第一时间段内将材料沉积在衬底上，然后在第二压力下将材料沉积在衬底上持续第二段时间。压力的调制影响在等离子体环境中离子化的颗粒的电离和轨迹。在一个方面，本发明的方法允许在高压步骤期间在高纵横比特征的底部进行最佳沉积，并且在至少低压步骤期间在特征的侧壁上增加沉积。

6. 发明授权

US06287977B1 Method and apparatus for forming improved metal interconnects 失效
标题翻译：用于形成改进的金属互连的方法和装置
公开(公告)号：US06287977B1
公开(公告)日：2001-09-11
申请号：US09126890
申请日：1998-07-31
申请人： Imran Hashim , Tony Chiang , Barry Chin
发明人： Imran Hashim , Tony Chiang , Barry Chin
IPC分类号： H01L21302
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.
摘要翻译：公开了形成没有通孔到通孔泄漏电流并具有低电阻的铜互连的方法。在第一方面，在铜氧化物溅射蚀刻之前，在第一金属层上沉积阻挡层，以防止铜原子到达层间电介质，并在其中形成通孔到漏电流路径。在第二方面，在溅射蚀刻之前，在第一金属层上沉积封盖电介质阻挡层。在溅射蚀刻期间，封盖电介质阻挡层重新分布在层间电介质的侧壁上，防止溅射蚀刻的铜原子到达层间电介质并在其中形成通孔到通孔泄漏路径。在第三方面，在溅射蚀刻之前，在第一金属层上沉积封盖介电阻挡层和阻挡层，以防止在溅射蚀刻期间产生的铜原子到达层间电介质并形成通孔到通孔泄漏路径其中。

7. 发明授权

US06174811B1 Integrated deposition process for copper metallization 失效
标题翻译：铜金属化的集成沉积工艺
公开(公告)号：US06174811B1
公开(公告)日：2001-01-16
申请号：US09204323
申请日：1998-12-02
申请人： Peijun Ding , Imran Hashim , Barry Chin , Bingxi Sun
发明人： Peijun Ding , Imran Hashim , Barry Chin , Bingxi Sun
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , C23C14/0641 , C23C14/165 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L21/76882
摘要： Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.
摘要翻译：金属化处理序列被提供用于形成可靠的互连，包括线，通孔和触点。首先在图案化衬底上形成初始阻挡层，例如Ta或TaN，然后使用高密度等离子体PVD技术形成晶种层。然后使用1）电镀，2）PVD回流，3）CVD，然后PVD回流或4）CVD来填充该结构。

8. 发明申请

US20050272254A1 Method of depositing low resistivity barrier layers for copper interconnects 审中-公开
标题翻译：沉积用于铜互连的低电阻阻挡层的方法
公开(公告)号：US20050272254A1
公开(公告)日：2005-12-08
申请号：US11184404
申请日：2005-07-18
申请人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
发明人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
IPC分类号： C23C14/06 , C23C14/16 , C23C14/32 , H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02183 , C23C14/0641 , C23C14/165 , C23C14/541 , C23C14/5806 , H01L21/02266 , H01L21/2855 , H01L21/318 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876
摘要： We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 μΩ cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.
摘要翻译：我们已经发现了一种提供大约约2埃至大约100埃的Ta N种子层的薄膜的方法，当钽沉积在Ta上时可用于诱导形成α钽， SUB> N 种子层。此外，Ta N N种子层在30μΩ·cm的范围内显示低电阻率，并且可以在不存在α钽层的情况下用作低电阻率阻挡层。在该方法的一个实施方案中，TaN膜在其表面上形成Ta N N种子层。在该方法的另一个实施方案中，在其表面上改变Ta膜以形成Ta N N种子层。

9. 发明申请

US20050173239A1 End point detection for sputtering and resputtering 失效
标题翻译：溅射和再溅射的终点检测
公开(公告)号：US20050173239A1
公开(公告)日：2005-08-11
申请号：US10659902
申请日：2003-09-11
申请人： Sasson Somekh , Marc Schweitzer , John Forster , Zheng Xu , Roderick Mosely , Barry Chin , Howard Grunes
发明人： Sasson Somekh , Marc Schweitzer , John Forster , Zheng Xu , Roderick Mosely , Barry Chin , Howard Grunes
IPC分类号： C23C14/04 , C23C14/16 , C23C14/32 , C23C14/54 , C23C14/58 , G01N21/68 , H01J37/32 , H01L21/285 , H01L21/66 , H01L21/768
CPC分类号： C23C14/544 , C23C14/046 , C23C14/165 , C23C14/5833 , C23C14/5873 , G01N21/68 , H01J37/321 , H01J37/32477 , H01J37/32935 , H01J37/32963 , H01J37/3455 , H01L21/2855 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： Plasma etching or resputtering of a layer of sputtered materials including opaque metal conductor materials may be controlled in a sputter reactor system. In one embodiment, resputtering of a sputter deposited layer is performed after material has been sputtered deposited and while additional material is being sputter deposited onto a substrate. A path positioned within a chamber of the system directs light or other radiation emitted by the plasma to a chamber window or other optical view-port which is protected by a shield against deposition by the conductor material. In one embodiment, the radiation path is folded to reflect plasma light around the chamber shield and through the window to a detector positioned outside the chamber window. Although deposition material may be deposited onto portions of the folded radiation path, in many applications, the deposition material will be sufficiently reflective to permit the emission spectra to be detected by a spectrometer or other suitable detector without significant signal loss. The etching or resputtering may be terminated when the detector detects that an underlying layer has been reached or when some other suitable process point has been reached.
摘要翻译：可以在溅射反应器系统中控制包括不透明金属导体材料的溅射材料层的等离子体蚀刻或再溅射。在一个实施例中，溅射沉积层的溅射在材料溅射沉积之后进行，并且另外的材料被溅射沉积到衬底上。位于系统的腔室内的路径将等离子体发射的光或其他辐射引导到腔室窗口或其他光学视图端口，其被屏蔽物保护以防止被导体材料沉积。在一个实施例中，辐射路径被折叠以将等离子体光围绕室屏蔽件并且通过窗口反射到位于室窗口外部的检测器。虽然沉积材料可以沉积在折叠辐射路径的部分上，但是在许多应用中，沉积材料将被充分反射，以允许发射光谱由光谱仪或其它合适的检测器检测，而没有显着的信号损失。当检测器检测到已经到达下层或者当达到某些其它合适的处理点时，蚀刻或再溅射可以被终止。

10. 发明申请

US20050031784A1 Barrier layer for electroplating processes 审中-公开
标题翻译：电镀工艺的屏障层
公开(公告)号：US20050031784A1
公开(公告)日：2005-02-10
申请号：US10931865
申请日：2004-09-01
申请人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
发明人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
IPC分类号： C25D5/34 , C25D3/00 , C25D7/12 , H01L21/28 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , C23C14/00 , H05H1/24
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
摘要翻译：本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。本发明的另一方面提供了一种用于在基板上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构。

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