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1. 发明申请

US20110018109A1 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation 有权
标题翻译：深硅通孔用于电路和器件的接地，发射极的镇流和隔离
公开(公告)号：US20110018109A1
公开(公告)日：2011-01-27
申请号：US12800663
申请日：2010-05-20
申请人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
发明人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
IPC分类号： H01L29/06 , H01L23/532 , H01L21/768
CPC分类号： H01L21/743 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
摘要翻译：根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。深硅通孔可以包括侧壁电介质层和底部导电层。还公开了制造深硅通孔的方法。深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

2. 发明授权

US08098351B2 Self-planarized passivation dielectric for liquid crystal on silicon structure and related method 有权
标题翻译：用于硅晶体结构的自平面钝化电介质及相关方法
公开(公告)号：US08098351B2
公开(公告)日：2012-01-17
申请号：US12157881
申请日：2008-06-13
申请人： Arjun Kar-Roy
发明人： Arjun Kar-Roy
IPC分类号： G02F1/1333
CPC分类号： G02F1/136277 , G02F2001/133357
摘要： According to an exemplary embodiment, a liquid crystal on silicon (LCoS) structure includes a number of pixel electrodes overlying an interlayer dielectric, where diagonally adjacent pixel electrodes are separated by a gap. The LCoS structure further includes a self-planarizing passivation dielectric situated over the pixel electrodes and in the gap, where the self-planarizing passivation dielectric has a selected thickness. The self-planarizing passivation dielectric can be an Oxide-Nitride-Oxide (ONO) stack. The selected thickness of the self-planarizing passivation dielectric causes the self-planarizing passivation dielectric to have a substantially planar top surface. In one embodiment, the thickness of the self-planarizing passivation dielectric can be approximately equal to twice a width of the gap.
摘要翻译：根据示例性实施例，液晶硅（LCoS）结构包括覆盖层间电介质的多个像素电极，其中对角相邻的像素电极被间隙隔开。 LCoS结构还包括位于像素电极之上和间隙中的自平坦化钝化电介质，其中自平面化钝化电介质具有选定的厚度。自平坦化钝化电介质可以是氧化物 - 氮化物 - 氧化物（ONO）堆叠。自平坦化钝化电介质的选定厚度导致自平坦化钝化电介质具有基本平坦的顶表面。在一个实施例中，自平面化钝化电介质的厚度可以近似等于间隙宽度的两倍。

3. 发明授权

US07078310B1 Method for fabricating a high density composite MIM capacitor with flexible routing in semiconductor dies 有权
标题翻译：在半导体管芯中制造具有柔性布线的高密度复合MIM电容器的方法
公开(公告)号：US07078310B1
公开(公告)日：2006-07-18
申请号：US10850187
申请日：2004-05-19
申请人： Arjun Kar-Roy , Marco Racanelli , Paul Kempf
发明人： Arjun Kar-Roy , Marco Racanelli , Paul Kempf
IPC分类号： H01L21/20
CPC分类号： H01L28/60 , H01L21/76838 , H01L23/5223 , H01L27/0805 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a shared electrode of the lower MIM capacitor and an upper MIM capacitor. The structure further comprises an electrode of the upper MIM capacitor situated over the shared electrode. The electrode of the upper MIM capacitor is coupled to the electrode of the lower MIM capacitor through vias and a second interconnect metal layer. In one embodiment, the electrode of the upper MIM capacitor can be divided into two or more segments to allow additional paths for connectivity to reduce the resistance of an electrode of the composite MIM capacitor. In other embodiments, a method for fabricating various embodiments of the composite MIM capacitor is disclosed.
摘要翻译：根据一个实施例，结构包括位于半导体管芯的第一互连金属层中的下部MIM电容器的电极。该结构还包括下MIM电容器的共享电极和上MIM电容器。该结构还包括位于共享电极上方的上MIM电容器的电极。上MIM电容器的电极通过通孔和第二互连金属层耦合到下MIM电容器的电极。在一个实施例中，上MIM电容器的电极可以被划分成两个或更多个段，以允许用于连接的附加路径来降低复合MIM电容器的电极的电阻。在其他实施例中，公开了一种用于制造复合MIM电容器的各种实施例的方法。

4. 发明授权

US08598713B2 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation 有权
标题翻译：深硅通孔用于电路和器件的接地，发射极的镇流和隔离
公开(公告)号：US08598713B2
公开(公告)日：2013-12-03
申请号：US12800663
申请日：2010-05-20
申请人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
发明人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/743 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
摘要翻译：根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。深硅通孔可以包括侧壁电介质层和底部导电层。还公开了制造深硅通孔的方法。深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

5. 发明授权

US07589009B1 Method for fabricating a top conductive layer in a semiconductor die and related structure 失效
标题翻译：在半导体管芯中制造顶部导电层的方法和相关结构
公开(公告)号：US07589009B1
公开(公告)日：2009-09-15
申请号：US11641925
申请日：2006-12-18
申请人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David J. Howard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
摘要翻译：根据示例性实施例，用于在半导体管芯中制造顶部导电层的方法包括：通过半导体管芯的通孔区域中的至少一个层间电介质层开口形成贯通晶片。该方法还包括通过半导体管芯的衬底经由开口延伸穿透晶片以达到目标深度。该方法还包括通过开孔通过晶片的导电层形成贯通晶片，同时在暴露的顶部金属片上形成顶部导电层。

6. 发明授权

US07052966B2 Deep N wells in triple well structures and method for fabricating same 有权
标题翻译：三井结构中的深N井及其制造方法
公开(公告)号：US07052966B2
公开(公告)日：2006-05-30
申请号：US10411054
申请日：2003-04-09
申请人： Arjun Kar-Roy , Marco Racanelli , Jinshu Zhang
发明人： Arjun Kar-Roy , Marco Racanelli , Jinshu Zhang
IPC分类号： H01L21/77
CPC分类号： H01L21/761 , H01L21/74 , H01L21/823878 , H01L21/823892 , H01L27/0928
摘要： A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.
摘要翻译：一种用于在半导体管芯中制造结构的方法包括以下步骤：在衬底中注入深N阱，在衬底上沉积外延层，并在深N阱上形成P阱和横向隔离N，其中，横向隔离N阱和P阱在衬底和外延层中制造，并且其中横向隔离N阱横向围绕P阱，并且其中深N阱和横向隔离N良好地电隔离P阱。植入深N阱可以包括在衬底上沉积屏幕氧化物层，在屏幕氧化物层上形成掩模，在衬底中注入深N阱，去除掩模和去除屏蔽氧化物层的步骤。沉积外延层可以包括在衬底上沉积单晶硅。

7. 发明授权

US07041569B1 Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies 有权
标题翻译：用于制造半导体芯片中具有降低的电压依赖性的高密度复合MIM电容器的方法
公开(公告)号：US07041569B1
公开(公告)日：2006-05-09
申请号：US10712067
申请日：2003-11-13
申请人： Arjun Kar-Roy , Marco Racanelli , David Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David Howard
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/76838 , H01L27/0805
摘要： According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.
摘要翻译：根据所公开的实施例，复合MIM电容器包括位于半导体管芯的下互连金属层中的下MIM电容器的下电极。复合MIM电容器还包括位于下层间电介质中的下MIM电容器的上电极，其中下层间电介质将下互连金属层与上互连金属层分开。上MIM电容器的下电极位于上互连金属层中。上MIM电容器的上电极位于上层间电介质中，其又位于上互连金属层上。下MIM电容器的上电极连接到上MIM电容器的下电极，而下MIM电容器的下电极连接到上MIM电容器的上电极。

8. 发明授权

US06777777B1 High density composite MIM capacitor with flexible routing in semiconductor dies 有权
标题翻译：高密度复合MIM电容器，在半导体芯片中具有灵活的布线
公开(公告)号：US06777777B1
公开(公告)日：2004-08-17
申请号：US10447397
申请日：2003-05-28
申请人： Arjun Kar-Roy , Marco Racanelli , Paul Kempf
发明人： Arjun Kar-Roy , Marco Racanelli , Paul Kempf
IPC分类号： H01L2900
CPC分类号： H01L28/60 , H01L21/76838 , H01L23/5223 , H01L27/0805 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a shared electrode of the lower MIM capacitor and an upper MIM capacitor. The structure further comprises an electrode of the upper MIM capacitor situated over the shared electrode. The electrode of the upper MIM capacitor is coupled to the electrode of the lower MIM capacitor through vias and a second interconnect metal layer. In one embodiment, the electrode of the upper MIM capacitor can be divided into two or more segments to allow additional paths for connectivity to reduce the resistance of an electrode of the composite MIM capacitor. In other embodiments, a method for fabricating various embodiments of the composite MIM capacitor is disclosed.
摘要翻译：根据一个实施例，结构包括位于半导体管芯的第一互连金属层中的下部MIM电容器的电极。该结构还包括下MIM电容器的共享电极和上MIM电容器。该结构还包括位于共享电极上方的上MIM电容器的电极。上MIM电容器的电极通过通孔和第二互连金属层耦合到下MIM电容器的电极。在一个实施例中，上MIM电容器的电极可以被分成两个或多个段，以允许用于连接的附加路径来降低复合MIM电容器的电极的电阻。在其他实施例中，公开了一种用于制造复合MIM电容器的各种实施例的方法。

9. 发明授权

US06180976B2 Thin-film capacitors and methods for forming the same 有权
标题翻译：薄膜电容器及其形成方法
公开(公告)号：US06180976B2
公开(公告)日：2001-01-30
申请号：US09241728
申请日：1999-02-02
申请人： Arjun Kar Roy
发明人： Arjun Kar Roy
IPC分类号： H01L31119
CPC分类号： H01L28/55 , H01L21/31053 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An improved thin-film capacitor and methods for forming the same on a surface of a substrate are disclosed. The capacitor includes a bottom conducting plate formed by depositing conductive material within a trench of an insulating layer and planarizing the conducting and insulating layers. A dielectric film is then deposited on the substrate surface, such that at least a portion of the dielectric material remains over the bottom conducting plate. A second conductive layer is then deposited over the surface of the substrate, patterned and etched such that at least a portion of the second conducting material resides over at least a portion of the dielectric material.
摘要翻译：公开了一种改进的薄膜电容器及其在基板表面上的形成方法。电容器包括通过在绝缘层的沟槽内沉积导电材料并平坦化导电层和绝缘层而形成的底部导电板。然后在衬底表面上沉积电介质膜，使得电介质材料的至少一部分保留在底部导电板上。然后将第二导电层沉积在衬底的表面上，被图案化和蚀刻，使得第二导电材料的至少一部分驻留在电介质材料的至少一部分上。

10. 发明授权

US09136157B1 Deep N wells in triple well structures 有权
标题翻译：三井结构中的深N井
公开(公告)号：US09136157B1
公开(公告)日：2015-09-15
申请号：US11198425
申请日：2005-08-05
申请人： Arjun Kar-Roy , Marco Racanelli , Jinshu Zhang
发明人： Arjun Kar-Roy , Marco Racanelli , Jinshu Zhang
IPC分类号： H01L21/761 , H01L27/092
CPC分类号： H01L21/761 , H01L21/74 , H01L21/823878 , H01L21/823892 , H01L27/0928
摘要： A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.
摘要翻译：一种用于在半导体管芯中制造结构的方法包括以下步骤：在衬底中注入深N阱，在衬底上沉积外延层，并在深N阱上形成P阱和横向隔离N，其中，横向隔离N阱和P阱在衬底和外延层中制造，并且其中横向隔离N阱横向围绕P阱，并且其中深N阱和横向隔离N良好地电隔离P阱。植入深N阱可以包括在衬底上沉积屏幕氧化物层，在屏幕氧化物层上形成掩模，在衬底中注入深N阱，去除掩模和去除屏蔽氧化物层的步骤。沉积外延层可以包括在衬底上沉积单晶硅。

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