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1. 发明申请

US20110018109A1 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation 有权
标题翻译：深硅通孔用于电路和器件的接地，发射极的镇流和隔离
公开(公告)号：US20110018109A1
公开(公告)日：2011-01-27
申请号：US12800663
申请日：2010-05-20
申请人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
发明人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
IPC分类号： H01L29/06 , H01L23/532 , H01L21/768
CPC分类号： H01L21/743 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
摘要翻译：根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。深硅通孔可以包括侧壁电介质层和底部导电层。还公开了制造深硅通孔的方法。深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

2. 发明授权

US08598713B2 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation 有权
标题翻译：深硅通孔用于电路和器件的接地，发射极的镇流和隔离
公开(公告)号：US08598713B2
公开(公告)日：2013-12-03
申请号：US12800663
申请日：2010-05-20
申请人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
发明人： Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/743 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
摘要翻译：根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。深硅通孔可以包括侧壁电介质层和底部导电层。还公开了制造深硅通孔的方法。深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

3. 发明授权

US06680521B1 High density composite MIM capacitor with reduced voltage dependence in semiconductor dies 有权
标题翻译：具有降低电压依赖性的半导体芯片的高密度复合MIM电容器
公开(公告)号：US06680521B1
公开(公告)日：2004-01-20
申请号：US10410937
申请日：2003-04-09
申请人： Arjun Kar-Roy , Marco Racanelli , David Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David Howard
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L21/76838 , H01L27/0805
摘要： According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.
摘要翻译：根据所公开的实施例，复合MIM电容器包括位于半导体管芯的下互连金属层中的下MIM电容器的下电极。复合MIM电容器还包括位于下层间电介质中的下MIM电容器的上电极，其中下层间电介质将下互连金属层与上互连金属层分开。上MIM电容器的下电极位于上互连金属层中。上MIM电容器的上电极位于上层间电介质中，其又位于上互连金属层上。下MIM电容器的上电极连接到上MIM电容器的下电极，而下MIM电容器的下电极连接到上MIM电容器的上电极。

4. 发明授权

US07041569B1 Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies 有权
标题翻译：用于制造半导体芯片中具有降低的电压依赖性的高密度复合MIM电容器的方法
公开(公告)号：US07041569B1
公开(公告)日：2006-05-09
申请号：US10712067
申请日：2003-11-13
申请人： Arjun Kar-Roy , Marco Racanelli , David Howard
发明人： Arjun Kar-Roy , Marco Racanelli , David Howard
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/76838 , H01L27/0805
摘要： According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.
摘要翻译：根据所公开的实施例，复合MIM电容器包括位于半导体管芯的下互连金属层中的下MIM电容器的下电极。复合MIM电容器还包括位于下层间电介质中的下MIM电容器的上电极，其中下层间电介质将下互连金属层与上互连金属层分开。上MIM电容器的下电极位于上互连金属层中。上MIM电容器的上电极位于上层间电介质中，其又位于上互连金属层上。下MIM电容器的上电极连接到上MIM电容器的下电极，而下MIM电容器的下电极连接到上MIM电容器的上电极。

5. 发明授权

US06943414B2 Method for fabricating a metal resistor in an IC chip and related structure 有权
标题翻译： IC芯片中金属电阻器的制造方法及相关结构
公开(公告)号：US06943414B2
公开(公告)日：2005-09-13
申请号：US10073751
申请日：2002-02-09
申请人： Arjun Kar Roy , David Howard , Q.Z. Liu
发明人： Arjun Kar Roy , David Howard , Q.Z. Liu
IPC分类号： H01L21/02 , H01L27/08 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L28/24 , H01L27/0802
摘要： According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer. The integrated circuit chip further comprises a second intermediate via connected to a second terminal of the metal resistor, where the second intermediate via is further connected to a second metal segment patterned in the second interconnect metal layer.
摘要翻译：根据一个示例性实施例，集成电路芯片包括第一互连金属层。集成电路芯片还包括位于第一互连金属层上的第一中间电介质层。集成电路芯片还包括位于第一金属间介电层之上并位于第二金属间介电层下方的金属电阻器。集成电路芯片还包括在第二金属间介电层上的第二互连金属层。集成电路芯片还包括连接到金属电阻器的第一端子的第一中间通孔，其中第一中间通孔进一步连接到在第二互连金属层中图案化的第一金属段。集成电路芯片还包括连接到金属电阻器的第二端子的第二中间通路，其中第二中间通路进一步连接到在第二互连金属层中图案化的第二金属段。

6. 发明授权

US07064361B1 NPN transistor having reduced extrinsic base resistance and improved manufacturability 有权
标题翻译： NPN晶体管具有降低的外部基极电阻和改进的可制造性
公开(公告)号：US07064361B1
公开(公告)日：2006-06-20
申请号：US10865634
申请日：2004-06-10
申请人： David Howard , Marco Racanelli , Greg D. U'Ren
发明人： David Howard , Marco Racanelli , Greg D. U'Ren
IPC分类号： H01L29/739
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/1004 , H01L29/167 , H01L29/66242 , H01L29/66272
摘要： According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.
摘要翻译：根据一个示例性实施例，NPN双极晶体管包括位于集电极上方的基极层，其中基极层包含本征基极区域和外部基极区域。 NPN双极晶体管可以是例如NPN硅 - 锗异质结双极晶体管。基层可以是例如硅 - 锗。根据该示例性实施例，NPN双极晶体管还包括位于基极层之上的覆盖层，其中覆盖层的一部分位于外部本体区域之上，并且其中覆盖层的位于外部基极区域之上的部分包括铟掺杂剂。盖层可以是例如多晶硅。根据该示例性实施例，NPN双极晶体管还可以包括位于本征基极区域上方的发射极。发射极可以是例如多晶硅。

7. 发明授权

US07235861B1 NPN transistor having reduced extrinsic base resistance and improved manufacturability 有权
标题翻译： NPN晶体管具有降低的外部基极电阻和改进的可制造性
公开(公告)号：US07235861B1
公开(公告)日：2007-06-26
申请号：US11003572
申请日：2004-12-02
申请人： David Howard , Marco Racanelli , Greg D. U'Ren
发明人： David Howard , Marco Racanelli , Greg D. U'Ren
IPC分类号： H01L29/73
CPC分类号： H01L29/66287 , H01L29/66242
摘要： A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a cap layer situated over the base layer. According to this embodiment, the method for fabricating the NPN bipolar transistor further comprises fabricating an emitter over the base layer, where the emitter defines an intrinsic and an extrinsic base region of the base layer. The emitter may comprise, for example, polycrystalline silicon. The method for fabricating the NPN bipolar transistor further comprises implanting germanium in the extrinsic base region of the base layer so as to make the extrinsic base region substantially amorphous. The method for fabricating the NPN bipolar transistor further comprises implanting boron in the extrinsic base region of the base layer.
摘要翻译：一种用于制造NPN双极晶体管的方法，包括在衬底的顶表面上形成基层。 NPN双极晶体管可以是NPN硅 - 锗异质结双极晶体管。制造NPN双极晶体管的方法还可以包括位于基极层之上的覆盖层。根据该实施例，用于制造NPN双极晶体管的方法还包括在基极层上制造发射极，其中发射极限定基极层的本征和非本征基极区域。发射极可以包括例如多晶硅。制造NPN双极晶体管的方法还包括将锗掺杂在基层的外部基极区域中，以使外部基极区域基本上无定形。用于制造NPN双极晶体管的方法还包括在基层的外部基极区域中注入硼。

8. 发明授权

US06893931B1 Reducing extrinsic base resistance in an NPN transistor 有权
标题翻译：降低NPN晶体管的外部基极电阻
公开(公告)号：US06893931B1
公开(公告)日：2005-05-17
申请号：US10290955
申请日：2002-11-07
申请人： David Howard , Marco Racanelli , Greg D. U'Ren
发明人： David Howard , Marco Racanelli , Greg D. U'Ren
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a cap layer situated over the base layer. According to this embodiment, the method for fabricating the NPN bipolar transistor further comprises fabricating an emitter over the base layer, where the emitter defines an intrinsic and an extrinsic base region of the base layer. The emitter may comprise, for example, polycrystalline silicon. The method for fabricating the NPN bipolar transistor further comprises implanting germanium in the extrinsic base region of the base layer so as to make the extrinsic base region substantially amorphous. The method for fabricating the NPN bipolar transistor further comprises implanting boron in the extrinsic base region of the base layer.
摘要翻译：一种用于制造NPN双极晶体管的方法，包括在衬底的顶表面上形成基层。 NPN双极晶体管可以是NPN硅 - 锗异质结双极晶体管。制造NPN双极晶体管的方法还可以包括位于基极层之上的覆盖层。根据该实施例，用于制造NPN双极晶体管的方法还包括在基极层上制造发射极，其中发射极限定基极层的本征和非本征基极区域。发射极可以包括例如多晶硅。制造NPN双极晶体管的方法还包括将锗掺杂在基层的外部基极区域中，以使外部基极区域基本上无定形。用于制造NPN双极晶体管的方法还包括在基层的外部基极区域中注入硼。

9. 发明授权

US06830982B1 Method for reducing extrinsic base resistance and improving manufacturability in an NPN transistor 有权
标题翻译：降低外部碱性电阻并提高NPN晶体管可制造性的方法
公开(公告)号：US06830982B1
公开(公告)日：2004-12-14
申请号：US10290976
申请日：2002-11-07
申请人： David Howard , Marco Racanelli , Greg D. U'Ren
发明人： David Howard , Marco Racanelli , Greg D. U'Ren
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/1004 , H01L29/167 , H01L29/66242 , H01L29/66272
摘要： According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.
摘要翻译：根据一个示例性实施例，NPN双极晶体管包括位于集电极上方的基极层，其中基极层包含本征基极区域和外部基极区域。 NPN双极晶体管可以是例如NPN硅 - 锗异质结双极晶体管。基层可以是例如硅 - 锗。根据该示例性实施例，NPN双极晶体管还包括位于基极层之上的覆盖层，其中覆盖层的一部分位于外部本体区域之上，并且其中覆盖层的位于外部基极区域之上的部分包括铟掺杂剂。盖层可以是例如多晶硅。根据该示例性实施例，NPN双极晶体管还可以包括位于本征基极区域上方的发射极。发射极可以是例如多晶硅。

10. 发明申请

US20170367381A1 IN-BAG PROCESS FOR COOKING OR PARTIALLY COOKING WATER-ABSORBING AND OTHER FOOD PRODUCTS IN A CONTINUOUS OVEN 审中-公开
公开(公告)号：US20170367381A1
公开(公告)日：2017-12-28
申请号：US15194811
申请日：2016-06-28
申请人： David Howard
发明人： David Howard
IPC分类号： A23L5/10 , B65D81/34 , A23L7/10
CPC分类号： A23L5/13 , A23L7/109 , A23L7/143 , A23L7/1975 , A23L11/01 , A23V2002/00 , B65D75/38 , B65D81/3415 , B65D81/343 , B65D2581/3404 , B65D2581/3422 , B65D2581/3427
摘要： A process for cooking rice, quinoa, couscous, pasta, beans, chick peas and other products which absorb water during the cooking process. The product is placed in sealed cooking bags along with a sufficient amount of liquid for absorption. The sealed bags are then conveyed through a continuous oven in which they are contacted with a superheated vapor cooking medium.

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