专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070197009A1 Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration 有权
标题翻译：使用聚集的间隔凹槽蚀刻（ASRE）整合来改善具有间隔凹槽的自对准硅化物扩展性的方法
公开(公告)号：US20070197009A1
公开(公告)日：2007-08-23
申请号：US11360897
申请日：2006-02-22
申请人： Anadi Srivastava , Mark Hall , Raghaw Rai , Jesse Yanez
发明人： Anadi Srivastava , Mark Hall , Raghaw Rai , Jesse Yanez
IPC分类号： H01L21/28
CPC分类号： H01L29/6656 , H01L21/28052 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor structure (201) is provided which comprises a semiconductor substrate (202), a gate (209) disposed on the semiconductor substrate, and a spacer (219) adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant (215) is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide (225) is formed which extends over the first and second lateral portions of the gate.
摘要翻译：提供了一种制造硅化栅（209）的方法。根据该方法，提供半导体结构（201），其包括半导体衬底（202），设置在半导体衬底上的栅极（209）和与栅极相邻的间隔物（219）。对该结构进行暴露栅极的第一横向部分的第一蚀刻。然后在与间隔物相邻的区域中产生植入物（215）。然后对该结构进行暴露栅电极的第二横向部分的第二蚀刻，并且形成在栅极的第一和第二横向部分上延伸的硅化物层（225）。

2. 发明授权

US07820539B2 Method for separately optimizing spacer width for two transistor groups using a recess spacer etch (RSE) integration 有权
标题翻译：使用凹槽间隔蚀刻（RSE）集成分别优化两个晶体管组的间隔物宽度的方法
公开(公告)号：US07820539B2
公开(公告)日：2010-10-26
申请号：US11364985
申请日：2006-02-28
申请人： Anadi Srivastava
发明人： Anadi Srivastava
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/84 , H01L21/823468
摘要： A method for making a semiconductor device is provided. In accordance with the method, a semiconductor structure is provided which comprises (a) a substrate (203), (b) first (219) and second (220) gate electrodes disposed over the substrate, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to said first and second gate electrodes, respectively. A first layer of photoresist (231) is disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered. The structure is then subjected to an etch which etches the first layer of photoresist and a portion of the first and second sets of spacer structures.
摘要翻译：提供一种制造半导体器件的方法。根据该方法，提供一种半导体结构，其包括：（a）设置在衬底上的衬底（203），（b）第一（219）和第二（220）栅电极，以及（c）第一（223）和分别与所述第一和第二栅电极相邻设置的第二（225）组间隔结构。第一层光致抗蚀剂（231）设置在结构上，使得第一组间隔结构被暴露并且第二组间隔结构被覆盖。然后对该结构进行蚀刻，蚀刻第一层光致抗蚀剂和第一组和第二组间隔结构的一部分。

3. 发明申请

US20070202675A1 Method for separately optimizing spacer width for two transistor groups using a recess spacer etch (RSE) integration 有权
标题翻译：使用凹槽间隔蚀刻（RSE）集成分别优化两个晶体管组的间隔物宽度的方法
公开(公告)号：US20070202675A1
公开(公告)日：2007-08-30
申请号：US11364985
申请日：2006-02-28
申请人： Anadi Srivastava
发明人： Anadi Srivastava
IPC分类号： H01L21/8234
CPC分类号： H01L21/84 , H01L21/823468
摘要： A method for making a semiconductor device is provided. In accordance with the method, a semiconductor structure is provided which comprises (a) a substrate (203), (b) first (219) and second (220) gate electrodes disposed over the substrate, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to said first and second gate electrodes, respectively. A first layer of photoresist (231) is disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered. The structure is then subjected to an etch which etches the first layer of photoresist and a portion of the first and second sets of spacer structures.
摘要翻译：提供一种制造半导体器件的方法。根据该方法，提供一种半导体结构，其包括：（a）设置在衬底上的衬底（203），（b）第一（219）和第二（220）栅电极，以及（c）第一（223）和分别与所述第一和第二栅电极相邻设置的第二（225）组间隔结构。第一层光致抗蚀剂（231）设置在结构上，使得第一组间隔结构被暴露并且第二组间隔结构被覆盖。然后对该结构进行蚀刻，蚀刻第一层光致抗蚀剂和第一组和第二组间隔结构的一部分。

4. 发明申请

US20070197011A1 Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration 审中-公开
标题翻译：使用独立凹陷蚀刻集成来改善具有间隔凹槽的自对准硅化物扩展性的方法
公开(公告)号：US20070197011A1
公开(公告)日：2007-08-23
申请号：US11360318
申请日：2006-02-22
申请人： Anadi Srivastava , Paul Grudowski , Dharmesh Jawarani , Rode Mora
发明人： Anadi Srivastava , Paul Grudowski , Dharmesh Jawarani , Rode Mora
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/76895 , H01L21/28052 , H01L29/665 , H01L29/6653
摘要： A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor substrate (202) is provided which has a gate (209) disposed thereon and which has a spacer (219) disposed adjacent to the gate. The spacer is subjected to a recess etch which exposes a lateral portion of the gate. An implant region (215) is then created adjacent to the spacer, and a layer of silicide (225) is formed which extends over the exposed lateral portion of the gate.
摘要翻译：提供了一种制造硅化栅（209）的方法。根据该方法，提供一种半导体衬底（202），其具有设置在其上的栅极（209），并且具有邻近栅极设置的间隔物（219）。间隔件进行凹口蚀刻，露出栅极的侧面部分。然后在间隔物附近产生注入区域（215），并且形成一层硅化物（225），其在栅极的暴露侧面部分上延伸。

5. 发明授权

US07902021B2 Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration 有权
标题翻译：使用凹槽间隔物集成分别优化两个或多个晶体管类别的间隔物宽度的方法
公开(公告)号：US07902021B2
公开(公告)日：2011-03-08
申请号：US11365059
申请日：2006-02-28
申请人： Anadi Srivastava
发明人： Anadi Srivastava
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823468 , H01L29/66772 , H01L29/78618 , Y10S438/911
摘要： A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.
摘要翻译：公开了制造半导体器件的方法。根据该方法，提供一种半导体结构，其包括（a）衬底（203），（b）设置在衬底上的第一和第二栅电极（219），第一和第二栅电极中的每一个具有第一和第二侧壁，以及（c）分别与第一和第二栅电极相邻设置的第一（223）和第二（225）组间隔结构。然后将第一层光致抗蚀剂（231）设置在结构上，使得第一组间隔结构被暴露并且第二组间隔结构被覆盖，之后第一组间隔结构被部分蚀刻。

6. 发明授权

US07563700B2 Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration 有权
标题翻译：使用聚集的间隔凹槽蚀刻（ASRE）整合来改善具有间隔凹槽的自对准硅化物扩展性的方法
公开(公告)号：US07563700B2
公开(公告)日：2009-07-21
申请号：US11360897
申请日：2006-02-22
申请人： Anadi Srivastava , Mark D. Hall , Raghaw S. Rai , Jesse Yanez
发明人： Anadi Srivastava , Mark D. Hall , Raghaw S. Rai , Jesse Yanez
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6656 , H01L21/28052 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor structure (201) is provided which comprises a semiconductor substrate (202), a gate (209) disposed on the semiconductor substrate, and a spacer (219) adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant (215) is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide (225) is formed which extends over the first and second lateral portions of the gate.
摘要翻译：提供了一种制造硅化栅（209）的方法。根据该方法，提供半导体结构（201），其包括半导体衬底（202），设置在半导体衬底上的栅极（209）和与栅极相邻的间隔物（219）。对该结构进行暴露栅极的第一横向部分的第一蚀刻。然后在与间隔物相邻的区域中产生植入物（215）。然后对该结构进行暴露栅电极的第二横向部分的第二蚀刻，并且形成在栅极的第一和第二横向部分上延伸的硅化物层（225）。

7. 发明申请

US20070202643A1 Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration 有权
标题翻译：使用凹槽间隔器集成来分别优化两个或多个晶体管类别的间隔物宽度的方法
公开(公告)号：US20070202643A1
公开(公告)日：2007-08-30
申请号：US11365059
申请日：2006-02-28
申请人： Anadi Srivastava
发明人： Anadi Srivastava
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823468 , H01L29/66772 , H01L29/78618 , Y10S438/911
摘要： A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (203), first and second gate electrodes (219) disposed over the substrate, each of said first and second gate electrodes having first and second sidewalls, and first (223) and second (225) sets of spacer structures disposed adjacent to said first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.
摘要翻译：本发明提供制造半导体器件的方法。根据该方法，提供了一种半导体结构，其包括衬底（203），设置在衬底上的第一和第二栅电极（219），所述第一和第二栅电极中的每一个具有第一和第二侧壁，以及第一（223 ）和分别与所述第一和第二栅电极相邻设置的第二（225）组间隔结构。然后将第一层光致抗蚀剂（231）设置在结构上，使得第一组间隔结构被暴露并且第二组间隔结构被覆盖，之后第一组间隔结构被部分蚀刻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式