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1. 发明申请

US20130326467A1 APPLICATION QUALITY PARAMETER MEASUREMENT-BASED DEVELOPMENT 有权
标题翻译：基于应用质量参数测量的开发
公开(公告)号：US20130326467A1
公开(公告)日：2013-12-05
申请号：US13485820
申请日：2012-05-31
申请人： Mini Nair , Pankaj Kachrulal Sarda , Anand Rengasamy , Alok Jain , Srivatsan Kidambi , Vivek Dalvi , A.R.K. Vamsee
发明人： Mini Nair , Pankaj Kachrulal Sarda , Anand Rengasamy , Alok Jain , Srivatsan Kidambi , Vivek Dalvi , A.R.K. Vamsee
IPC分类号： G06F9/44
CPC分类号： G06F11/3664
摘要： A development environment provides warnings based on one or more application categories set for an application. Each warning has a trigger threshold and a warning action. Different application categories have different warnings. The development environment proactively tests for trigger conditions and provides triggered warnings within a workflow that includes application designing, code editing, building, and running. For instance, a Social Networking application whose start-up time is greater than desired for Social Networking applications will trigger a warning. Password Manager or Finance applications that should use a more secure approach to store user data will trigger a warning not given to applications in other categories. A News application may trigger a warning from the development environment that application content is not easily readable if a user switches to a light color theme on a device. The application category is selected by the developer or set proactively by the development environment.
摘要翻译：开发环境基于为应用程序设置的一个或多个应用程序类别提供警告。每个警告都有触发阈值和警告动作。不同的应用类别有不同的警告。开发环境主动测试触发条件，并在工作流中提供触发警告，包括应用程序设计，代码编辑，构建和运行。例如，社交网络应用程序的启动时间大于社交网络应用程序所需的时间将触发警告。密码管理器或财务应用程序应使用更安全的方法来存储用户数据将触发不给予其他类别的应用程序的警告。新闻应用程序可能会触发开发环境的警告，如果用户切换到设备上的浅色主题，则应用程序内容不容易读取。应用程序类别由开发人员选择或由开发环境主动设置。

2. 发明授权

US07601269B2 On-chip sample preparation for whole blood analysis 失效
公开(公告)号：US07601269B2
公开(公告)日：2009-10-13
申请号：US12327204
申请日：2008-12-03
申请人： Chong H. Ahn , Aniruddha Puntambekar , Alok Jain , Jungyoup Han
发明人： Chong H. Ahn , Aniruddha Puntambekar , Alok Jain , Jungyoup Han
IPC分类号： B01D37/00 , B01L11/00
CPC分类号： B01D45/00 , B01D21/283 , B01L3/502746 , B01L3/502753 , B01L3/502761 , B01L3/502784 , B01L2200/0668 , B01L2200/146 , B01L2300/0816 , B01L2300/0861 , B01L2400/0487 , B01L2400/084 , B01L2400/086 , G01N33/491
摘要： A novel filter-less separation technique for separating suspended particles from a solution is disclosed. More specifically, an on-chip bioparticle separator is disclosed, which relies on the differential force exerted by application of a series of high magnitude, short duration pressure pulses on bioparticles in suspension within microchannels, resulting in separation of suspended bioparticles. The filter-less separation technique is inherently suited to μTAS (Micro Total Analysis System) since it exploits uniquely microscale phenomena to achieve separation. The on-chip bioparticle separator can be easily integrated with a disposable biochip, can be fabricated using low-cost, rapid manufacturing techniques, and can provide high performance for separation of bioparticles without the use of specialized or expensive equipment. Embodiments of the present invention address a significant challenge in the development of disposable microfluidic biochips, specifically, providing a reliable solution for separating bioparticles in a microfluidic system that may be immediately applied for a variety of microfluidic biochip applications.

3. 发明授权

US06802944B2 High density plasma CVD process for gapfill into high aspect ratio features 有权
标题翻译：高密度等离子体CVD工艺，用于间隙填充到高纵横比特征
公开(公告)号：US06802944B2
公开(公告)日：2004-10-12
申请号：US10279961
申请日：2002-10-23
申请人： Farhan Ahmad , Michael Awdshiew , Alok Jain , Bikram Kapoor
发明人： Farhan Ahmad , Michael Awdshiew , Alok Jain , Bikram Kapoor
IPC分类号： C23C1434
CPC分类号： H01L21/02129 , C23C16/045 , C23C16/401 , C23C16/505 , H01L21/02131 , H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/31625 , H01L21/31633 , H01L21/76837
摘要： A method of depositing a film on a substrate. In one embodiment, the method includes depositing a first portion of the film using a high density plasma to partially fill a gap formed between adjacent features formed on the substrate. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step that forms a plasma from a sputtering agent introduced into the processing chamber and biases the plasma towards the substrate and a subsequent chemical etch step that forms a plasma from a reactive etchant gas introduced into the processing chamber. After the etching sequence is complete, a second portion of the film is deposited over the first portion using a high density plasma to further fill the gap.
摘要翻译：一种在衬底上沉积膜的方法。在一个实施例中，该方法包括使用高密度等离子体沉积膜的第一部分以部分地填充形成在衬底上形成的相邻特征之间的间隙。然后在间隙夹紧进入之前或不久之后停止膜沉积工艺，并且使用包括从溅射剂形成等离子体的第一物理蚀刻步骤的两步蚀刻工艺来蚀刻膜以加宽到间隙的入口引入处理室并将等离子体偏压到衬底，以及随后的化学蚀刻步骤，其从引入处理室的反应性蚀刻剂气体形成等离子体。在蚀刻顺序完成之后，使用高密度等离子体在第一部分上沉积膜的第二部分以进一步填充间隙。

4. 发明授权

US08612905B1 System method and apparatus for vacuity detection 有权
标题翻译：用于真空检测的系统方法和装置
公开(公告)号：US08612905B1
公开(公告)日：2013-12-17
申请号：US11972884
申请日：2008-01-11
申请人： Pradeep Goyal , Alok Jain , Manu Chopra , Anurag Gupta , Deepak Yadav
发明人： Pradeep Goyal , Alok Jain , Manu Chopra , Anurag Gupta , Deepak Yadav
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and apparatus for producing a vacuity detection report to reduce false positive verification results for digital circuits provided. In an exemplary embodiment, a design description of the digital design is generated. From the design description, a vacuity detection problem is derived by introducing an assertion into the design description. By introducing an assertion into the design description, the vacuity detection problem is solvable by formal assertion based verification engines. A verification engine is then used to solve the vacuity detection problem and produce a vacuity detection report. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
摘要翻译：一种用于产生真空检测报告以减少提供的数字电路的假阳性验证结果的方法和装置。在示例性实施例中，生成数字设计的设计描述。从设计描述中，通过在设计描述中引入断言来导出真空检测问题。通过在设计描述中引入断言，真实性检测问题可以通过基于形式断言的验证引擎来解决。然后使用验证引擎来解决真空检测问题，并产生真空检测报告。本摘要仅用于遵守允许读者快速确定本文所包含的披露的主题的抽象要求规则。本摘要以明确的理解提交，不会用于解释或限制权利要求的范围或含义。

5. 发明授权

US08316332B1 Constraint minimization method for formal verification 有权
标题翻译：用于形式验证的约束最小化方法
公开(公告)号：US08316332B1
公开(公告)日：2012-11-20
申请号：US12831497
申请日：2010-07-07
申请人： Pradeep Goyal , Alok Jain
发明人： Pradeep Goyal , Alok Jain
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present disclosure relates to a method for minimizing constraints in the formal verification of an integrated circuit design. The method may include obtaining an unisolated list of constraints initially comprising all known constraints for the integrated circuit design and obtaining an isolated list of constraints initially comprising none of the known constraints. The method may further include attempting to prove an assertion without the known constraints and determining if the assertion is valid. The method may further include updating the isolated list of constraints.
摘要翻译：本公开涉及一种用于最小化集成电路设计的形式验证中的约束的方法。该方法可以包括获得最初包括用于集成电路设计的所有已知约束的约束的非隔离列表，并且获得最初包括已知约束的约束的孤立列表。该方法还可以包括尝试在没有已知约束的情况下证明断言并且确定断言是否有效。该方法还可以包括更新孤立的约束列表。

6. 发明授权

US07229930B2 Selective etching of low-k dielectrics 失效
标题翻译：选择性蚀刻低k电介质
公开(公告)号：US07229930B2
公开(公告)日：2007-06-12
申请号：US10341693
申请日：2003-01-13
申请人： Alok Jain , Phui Fah Chong
发明人： Alok Jain , Phui Fah Chong
IPC分类号： H01L21/302
CPC分类号： H01L21/31138
摘要： The present invention provides a low-k dielectric etching process with high etching selectivities with respect to adjacent layers of other materials, such as an overlying photoresist mask and an underlying barrier/liner layer. The process comprises the step of exposing a portion of the low-k dielectric layer to a plasma of a process gas that includes a fluorocarbon gas having a relatively low fluorine to carbon ratio, a nitrogen-containing gas, and an inert gas, wherein a volumetric flow ratio of the nitrogen-containing gas to the fluorocarbon gas is greater than about 20:1. The process can be used to over etch the low-k dielectric layer to provide improved selectivity to the photoresist mask and the barrier/liner layer, reduced striations and reduced CD loss as compared with conventional low-k dielectric etching processes.
摘要翻译：本发明提供了相对于其它材料的相邻层（例如覆盖光致抗蚀剂掩模和下面的阻挡层/衬里层）具有高蚀刻选择性的低k电介质蚀刻工艺。该方法包括将低k电介质层的一部分暴露于包括具有相对低的氟碳比的氟碳气体的工艺气体的等离子体，含氮气体和惰性气体的步骤，其中含氮气体与碳氟化合物气体的体积流量比大于约20:1。与传统的低k电介质蚀刻工艺相比，该方法可以用于过蚀刻低k电介质层，以提供对光致抗蚀剂掩模和阻挡层/衬里层的改善的选择性，减少的条纹和降低的CD损耗。

7. 发明授权

US07047510B1 Method and system for partitioning an integrated circuit design 有权
标题翻译：集成电路设计分区方法及系统
公开(公告)号：US07047510B1
公开(公告)日：2006-05-16
申请号：US10422535
申请日：2003-04-23
申请人： Manu Chopra , Xiaoqun Du , Ronald H. Hardin , Alok Jain , Robert P. Kurshan , Pratik Mahajan , Ravi Prakash , Kavita Ravi
发明人： Manu Chopra , Xiaoqun Du , Ronald H. Hardin , Alok Jain , Robert P. Kurshan , Pratik Mahajan , Ravi Prakash , Kavita Ravi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is partitioned at the granularity of modules. In another embodiment, the design is partitioned at the granularity of instances. In a third embodiment, instances are grouped together, subject to a weight threshold, so as to form possibly overlapping partitions of instances that are contiguous in the design hierarchy, with the purpose of avoiding, to the extent possible, false negatives. In a further embodiment, the design is partitioned to avoid redundant partitions. In an embodiment, model checking is applied to one or more local properties in each partition. In another embodiment, simulation is used to verify each partition.
摘要翻译：一种通过划分验证集成电路设计的方法和系统。在一个实施例中，对设计进行分区，然后验证每个分区。在一个实施例中，设计以模块的粒度被划分。在另一个实施例中，以实例的粒度对设计进行分区。在第三实施例中，实例被分组在一起，受到权重阈值的限制，以便形成在设计层次结构中是连续的实例的可能重叠的分区，目的是尽可能避免假的否定。在另一实施例中，将该设计分区以避免冗余分区。在一个实施例中，模型检查被应用于每个分区中的一个或多个局部属性。在另一个实施例中，使用模拟来验证每个分区。

8. 发明授权

US09106763B2 Advertising ringtone coverage 有权
标题翻译：广告铃声覆盖
公开(公告)号：US09106763B2
公开(公告)日：2015-08-11
申请号：US13090555
申请日：2011-04-20
申请人： Michael J. Coleman , Alok Jain , Matthew D. Whitbourne
发明人： Michael J. Coleman , Alok Jain , Matthew D. Whitbourne
IPC分类号： G06Q10/00 , H04M1/725 , G06Q30/02
CPC分类号： H04M1/72569 , G06Q30/0242 , H04M1/7253
摘要： An apparatus, method and computer program for quantifying coverage of an advertising ringtone in a telephony system, the apparatus comprising: a receive component for receiving a request for an electronic device; a generate component, responsive to the receiver receiving the request, for playing the advertising ringtone on the electronic device; and a monitor component, responsive to the electronic device playing the advertising ringtone, for collecting coverage information from a personal device, wherein the monitor component comprises: a proximity component for identifying a local electronic resource; a select component, responsive to the proximity component identifying the local electronic resource, for determining the local electronic resource is the personal device; and a gather component, responsive to the select component determining the personal device, for gathering coverage information from the personal device.
摘要翻译：一种用于量化电话系统中的广告铃声的覆盖的装置，方法和计算机程序，所述装置包括：用于接收对电子设备的请求的接收组件; 响应于所述接收器接收到所述请求的生成部件，用于在所述电子设备上播放所述广告铃声; 以及响应于播放广告铃声的电子设备的监视器组件，用于从个人设备收集覆盖信息，其中所述监视器组件包括：用于识别本地电子资源的接近组件; 响应于识别本地电子资源的邻近部件，用于确定本地电子资源的选择部件是个人设备; 以及响应于所述选择组件确定所述个人设备的收集组件，用于从所述个人设备收集覆盖信息。

9. 发明申请

US20130326465A1 Portable Device Application Quality Parameter Measurement-Based Ratings 审中-公开
标题翻译：便携式设备应用质量参数测量评级
公开(公告)号：US20130326465A1
公开(公告)日：2013-12-05
申请号：US13489183
申请日：2012-06-05
申请人： Alok Jain , Vivek Dalvi , Mini Nair , Pankaj Kachrulal Sarda , Anand Rengasamy , Srivatsan Kidambi , A.R.K. Vamsee
发明人： Alok Jain , Vivek Dalvi , Mini Nair , Pankaj Kachrulal Sarda , Anand Rengasamy , Srivatsan Kidambi , A.R.K. Vamsee
IPC分类号： G06F9/44
CPC分类号： G06F8/77 , G06Q10/0639 , G06Q30/00
摘要： A development environment simulates conditions combining device states, events, hardware configurations, and usage scenarios, and applies specific rating criteria to arrive at individual quality parameter ratings. Ratings are provided for quality parameters such as user experience, cost awareness, battery friendliness, responsiveness, global readiness, device independence, application stability. For example, battery friendliness depends on criteria such as battery life in a specified usage scenario, whether unused peripherals are powered, whether application program interfaces designated as power-hungry are avoided, whether darker color themes can be chosen over lighter colors, and whether batching is used for network data communications. Some rating criteria are application-category-specific. For example, security is rated differently for a Finance application than a Music application. The development environment provides specific warnings to indicate ways in which portable device applications and other applications can improve the ratings they receive. Ratings can be published in an application marketplace.
摘要翻译：开发环境模拟结合设备状态，事件，硬件配置和使用场景的条件，并应用特定的评估标准来达到各个质量参数等级。提供了诸如用户体验，成本意识，电池友好性，响应性，全局准备，设备独立性，应用程序稳定性等质量参数的评级。例如，电池友好性取决于诸如在指定使用场景中的电池寿命，是否对未使用的外围设备供电的标准，是否避免指定为电源饥饿的应用程序接口，是否可以在较浅的颜色上选择较暗的颜色主题，以及是否配料用于网络数据通信。一些评级标准是应用类别特定的。例如，财务应用程序的安全性与音乐应用程序不同。开发环境提供特定的警告，指示便携式设备应用程序和其他应用程序可以提高他们收到的等级的方式。评级可以在应用程序市场中发布。

10. 发明授权

US08413088B1 Verification plans to merging design verification metrics 有权
标题翻译：合并设计验证指标的验证计划
公开(公告)号：US08413088B1
公开(公告)日：2013-04-02
申请号：US12426188
申请日：2009-04-17
申请人： Frank Armbruster , Sandeep Pagey , F. Erich Marschner , Dan Leibovich , Alok Jain , Axel Scherer , Yaron Peri-Glass
发明人： Frank Armbruster , Sandeep Pagey , F. Erich Marschner , Dan Leibovich , Alok Jain , Axel Scherer , Yaron Peri-Glass
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/2848 , G06F17/504
摘要： A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.
摘要翻译：提供了一种用于产生数字电路验证的方法和装置。在本发明的示例性实施例中，定义为验证计划的一部分的集成电路设计的多个验证范围。在由验证计划定义的两个或多个验证范围内执行多个验证运行。选择至少两次验证运行以将验证结果合并在一起。对于每个验证范围，像命名方案一样合并生成合并的验证结果，然后将其存储到合并数据库中。从合并的验证结果生成集成电路设计的验证报告。可以指定合并点，以便命名子树和子组可以在所选验证运行的不同验证范围之间合并。合并点可以将在模拟期间获得的检查和覆盖结果与在正式验证期间获得的检查和覆盖结果相结合。

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