专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07944751B2 Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture 有权
标题翻译：用于编程存储器单元的方法，特别是闪存类型以及相应的编程架构
公开(公告)号：US07944751B2
公开(公告)日：2011-05-17
申请号：US12556970
申请日：2009-09-10
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

2. 发明授权

US07606078B2 Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture 有权
标题翻译：用于编程存储器单元的方法，特别是闪存类型以及相应的编程架构
公开(公告)号：US07606078B2
公开(公告)日：2009-10-20
申请号：US11636382
申请日：2006-12-08
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C16/06
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

3. 发明授权

US07646655B2 Memory device with fail search and redundancy 有权
标题翻译：具有故障搜索和冗余的内存设备
公开(公告)号：US07646655B2
公开(公告)日：2010-01-12
申请号：US11780581
申请日：2007-07-20
申请人： Antonino Mondello , Alessandro Tumminia , Luigi Buono
发明人： Antonino Mondello , Alessandro Tumminia , Luigi Buono
IPC分类号： G11C7/00
CPC分类号： G11C29/48 , G11C16/04 , G11C29/16 , G11C29/4401 , G11C29/82
摘要： An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and substituting failed elements of the memory array with equivalent redundancy structures. A logic structure may detect and store memory array failures upstream of the output data path. Thereby, data collection relating to failures may be accomplished more quickly and without any interaction with the testing machine apart from communicating the end of the execution of the redundancy process.
摘要翻译：自动冗余系统可以利用现有的芯片上的微处理器管理系统来自主地执行，而不与外部测试机通信，操作：根据一个或多个预先建立的测试模式将数据写入存储器阵列，连续验证数据从存储器阵列读取，并用等效的冗余结构代替存储器阵列的故障元件。逻辑结构可以检测并存储在输出数据路径上游的存储器阵列故障。因此，与故障相关的数据收集可以更快地完成，并且除了传达冗余处理的执行结束之外，还不与测试机进行任何交互。

4. 发明申请

US20070147130A1 Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture 有权
标题翻译：用于编程存储器单元的方法，特别是闪存类型以及相应的编程架构
公开(公告)号：US20070147130A1
公开(公告)日：2007-06-28
申请号：US11636382
申请日：2006-12-08
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

5. 发明申请

US20100002521A1 Method for Programming of Memory Cells, in Particular of the Flash Type, and Corresponding Programming Architecture 有权
标题翻译：存储单元编程方法，特别是Flash类型的编程，以及相应的编程架构
公开(公告)号：US20100002521A1
公开(公告)日：2010-01-07
申请号：US12556970
申请日：2009-09-10
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

6. 发明申请

US20080049514A1 MEMORY DEVICE WITH A MANAGING MICROPROCESSOR SYSTEM AND AN ARCHITECTURE OF FAIL SEARCH AND AUTOMATIC REDUNDANCY 有权
标题翻译：具有管理微处理器系统的存储器件和无法搜索和自动冗余的架构
公开(公告)号：US20080049514A1
公开(公告)日：2008-02-28
申请号：US11780581
申请日：2007-07-20
申请人： Antonino Mondello , Alessandro Tumminia , Luigi Buono
发明人： Antonino Mondello , Alessandro Tumminia , Luigi Buono
IPC分类号： G11C29/12 , G11C11/34
CPC分类号： G11C29/48 , G11C16/04 , G11C29/16 , G11C29/4401 , G11C29/82
摘要： An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and substituting failed elements of the memory array with equivalent redundancy structures. A logic structure may detect and store memory array failures upstream of the output data path. Thereby, data collection relating to failures may be accomplished more quickly and without any interaction with the testing machine apart from communicating the end of the execution of the redundancy process.
摘要翻译：自动冗余系统可以利用现有的芯片上的微处理器管理系统来自主地执行，而不与外部测试机通信，操作：根据一个或多个预先建立的测试模式将数据写入存储器阵列，连续验证数据从存储器阵列读取，并用等效的冗余结构代替存储器阵列的故障元件。逻辑结构可以检测并存储在输出数据路径上游的存储器阵列故障。因此，与故障相关的数据收集可以更快地完成，并且除了传达冗余处理的执行结束之外，还不与测试机进行任何交互。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式