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1. 发明申请

US20070147130A1 Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture 有权
标题翻译：用于编程存储器单元的方法，特别是闪存类型以及相应的编程架构
公开(公告)号：US20070147130A1
公开(公告)日：2007-06-28
申请号：US11636382
申请日：2006-12-08
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

2. 发明申请

US20100002521A1 Method for Programming of Memory Cells, in Particular of the Flash Type, and Corresponding Programming Architecture 有权
标题翻译：存储单元编程方法，特别是Flash类型的编程，以及相应的编程架构
公开(公告)号：US20100002521A1
公开(公告)日：2010-01-07
申请号：US12556970
申请日：2009-09-10
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

3. 发明授权

US07944751B2 Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture 有权
标题翻译：用于编程存储器单元的方法，特别是闪存类型以及相应的编程架构
公开(公告)号：US07944751B2
公开(公告)日：2011-05-17
申请号：US12556970
申请日：2009-09-10
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

4. 发明授权

US07606078B2 Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture 有权
标题翻译：用于编程存储器单元的方法，特别是闪存类型以及相应的编程架构
公开(公告)号：US07606078B2
公开(公告)日：2009-10-20
申请号：US11636382
申请日：2006-12-08
申请人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
发明人： Davide Torrisi , Edoardo Nocita , Alessandro Tumminia
IPC分类号： G11C16/06
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/344
摘要： A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.
摘要翻译：描述了一种用于编程存储器单元的方法，特别是Flash类型的存储单元。根据该方法，利用第一并行性（M）执行验证，其中执行读取以确定一组存储器单元的状态，基于该程序并行性（np）执行编程并行性（np）的确定验证结果，以及使用编程并行性（np）执行的存储单元的实际编程。还描述了用于编程特别是闪存类型的存储器单元的架构。

5. 发明授权

US07773445B2 Reading method and circuit for a non-volatile memory device based on the adaptive generation of a reference electrical quantity 有权
标题翻译：基于自适应生成参考电量的非易失性存储器件的读取方法和电路
公开(公告)号：US07773445B2
公开(公告)日：2010-08-10
申请号：US12031645
申请日：2008-02-14
申请人： Giovanni Pagano , Pierluca Guarino , Edoardo Nocita
发明人： Giovanni Pagano , Pierluca Guarino , Edoardo Nocita
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/062 , G11C16/349 , G11C2207/063
摘要： A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a determination stage, which compares an array electrical quantity, correlated to a current flowing in the array memory cell, with a reference electrical quantity, and supplies an output signal indicative of the datum, based on the comparison; and a generator circuit, provided with an input receiving a target electrical quantity correlated to a current flowing in use in the reference memory cell, and an output, which supplies the reference electrical quantity with a controlled value close or equal to that of the target electrical quantity. The generator circuit is provided with a variable generator, and a control unit connected to, and designed to control, the variable generator so that it will generate the controlled value of the reference electrical quantity.
摘要翻译：一种用于确定存储在具有已知内容的至少一个参考存储器单元的非易失性存储器件的阵列存储器单元中的数据的值的电路。电路具有判定级，其将与阵列存储单元中流动的电流相关联的阵列电量与参考电量进行比较，并且基于该比较来提供表示基准的输出信号; 以及发生器电路，其具有接收与在基准存储单元中使用的电流相关的目标电量的输入端和输出端，所述输出以与所述目标电气接近或相等的受控值提供所述参考电量数量。发电机电路设置有可变发电机，以及连接到并被设计成控制可变发电机从而产生参考电量的受控值的控制单元。

6. 发明申请

US20080205158A1 READING METHOD AND CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE BASED ON THE ADAPTIVE GENERATION OF A REFERENCE ELECTRICAL QUANTITY 有权
标题翻译：基于参考电量自适应生成的非易失性存储器件的读取方法和电路
公开(公告)号：US20080205158A1
公开(公告)日：2008-08-28
申请号：US12031645
申请日：2008-02-14
申请人： Giovanni Pagano , Pierluca Guarino , Edoardo Nocita
发明人： Giovanni Pagano , Pierluca Guarino , Edoardo Nocita
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/067 , G11C7/062 , G11C16/349 , G11C2207/063
摘要： A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a determination stage, which compares an array electrical quantity, correlated to a current flowing in the array memory cell, with a reference electrical quantity, and supplies an output signal indicative of the datum, based on the comparison; and a generator circuit, provided with an input receiving a target electrical quantity correlated to a current flowing in use in the reference memory cell, and an output, which supplies the reference electrical quantity with a controlled value close or equal to that of the target electrical quantity. The generator circuit is provided with a variable generator, and a control unit connected to, and designed to control, the variable generator so that it will generate the controlled value of the reference electrical quantity.
摘要翻译：一种用于确定存储在具有已知内容的至少一个参考存储器单元的非易失性存储器件的阵列存储器单元中的数据的值的电路。电路具有判定级，其将与阵列存储单元中流动的电流相关联的阵列电量与参考电量进行比较，并且基于该比较来提供表示基准的输出信号; 以及发生器电路，其具有接收与在基准存储单元中使用的电流相关的目标电量的输入端和输出端，所述输出以与所述目标电气接近或相等的受控值提供所述参考电量数量。发电机电路设置有可变发电机，以及连接到并被设计成控制可变发电机从而产生参考电量的受控值的控制单元。

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