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1. 发明授权

US07474244B2 Current addition type digital analog converter 失效
标题翻译：当前加法型数字模拟转换器
公开(公告)号：US07474244B2
公开(公告)日：2009-01-06
申请号：US11889129
申请日：2007-08-09
申请人： Akira Kawabe , Akio Yokoyama
发明人： Akira Kawabe , Akio Yokoyama
IPC分类号： H03M1/66
CPC分类号： H03M1/002 , H03M1/745
摘要： A digital analog converter includes a current conversion section and a voltage conversion section. The current conversion section has a first output terminal and a second output terminal. The first output terminal outputs a first current and a second output terminal outputs a second current, the first current varying in value according to inputted digital data, the sum of the first current and the second current becoming a constant current. The voltage conversion section converts the first current to a corresponding first voltage and produces an offset voltage on the basis of the constant current and outputs the sum of the first voltage and the offset voltage as an output voltage.
摘要翻译：数字模拟转换器包括电流转换部分和电压转换部分。电流转换部分具有第一输出端和第二输出端。第一输出端子输出第一电流，第二输出端子输出第二电流，第一电流根据输入的数字数据变化值，第一电流和第二电流的和变为恒定电流。电压转换部将第一电流转换为对应的第一电压，并根据恒定电流产生偏移电压，并输出第一电压和偏移电压的和作为输出电压。

2. 发明授权

US07590041B2 Playback signal processing device 失效
标题翻译：播放信号处理装置
公开(公告)号：US07590041B2
公开(公告)日：2009-09-15
申请号：US11659238
申请日：2005-04-18
申请人： Akira Kawabe , Akira Yamamoto
发明人： Akira Kawabe , Akira Yamamoto
IPC分类号： G11B20/10
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10212 , G11B20/10222 , G11B20/10481 , G11B20/14 , G11B2220/2537 , H04L7/0029 , H04L25/03248
摘要： In a playback signal processing device for extracting, from an analog playback signal, playback data and a clock synchronized with the playback data, a digital equalizer 2 is disposed outside a clock extraction loop formed by an interpolator 3, a timing recovery circuit 4, and a control circuit 5. The digital equalizer 2 is provided between an A/D converter 1 and the interpolator 3 and performs equalization processing on digital playback data from the A/D converter 1 in accordance with the timing of a fixed clock CLK from a synthesizer 7. The coefficients of the digital equalizer 2 are updated by the control circuit 5 by using a coefficient setting device 6 according to frequency ratio information 4a from the timing recovery circuit 4. Accordingly, the clock extraction capability is enhanced in spite of the equalization processing on the playback signal by the digital equalizer.
摘要翻译：在用于从模拟播放信号提取回放数据和与重放数据同步的时钟的重放信号处理装置中，数字均衡器2设置在由内插器3，定时恢复电路4和控制电路5.数字均衡器2设置在A / D转换器1和内插器3之间，并且根据来自合成器的固定时钟CLK的定时对来自A / D转换器1的数字重放数据执行均衡处理数字均衡器2的系数由控制电路5通过使用根据来自定时恢复电路4的频率比信息4a的系数设置装置6来更新。因此，尽管进行均衡处理，时钟提取能力增强在数字均衡器上播放信号。

3. 发明申请

US20080037393A1 Playback Signal Processing Device 失效
标题翻译：播放信号处理设备
公开(公告)号：US20080037393A1
公开(公告)日：2008-02-14
申请号：US11659238
申请日：2005-04-18
申请人： Akira Kawabe , Akira Yamamoto
发明人： Akira Kawabe , Akira Yamamoto
IPC分类号： G11B19/02
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10212 , G11B20/10222 , G11B20/10481 , G11B20/14 , G11B2220/2537 , H04L7/0029 , H04L25/03248
摘要： In a playback signal processing device for extracting, from an analog playback signal, playback data and a clock synchronized with the playback data, a digital equalizer 2 is disposed outside a clock extraction loop formed by an interpolator 3, a timing recovery circuit 4, and a control circuit 5. The digital equalizer 2 is provided between an AID converter 1 and the interpolator 3 and performs equalization processing on digital playback data from the A/D converter 1 in accordance with the timing of a fixed clock CLK from a synthesizer 7. The coefficients of the digital equalizer 2 are updated by the control circuit 5 by using a coefficient setting device 6 according to frequency ratio information 4a from the timing recovery circuit 4. Accordingly, the clock extraction capability is enhanced in spite of the equalization processing on the playback signal by the digital equalizer.
摘要翻译：在用于从模拟播放信号提取回放数据和与重放数据同步的时钟的重放信号处理装置中，数字均衡器2设置在由内插器3，定时恢复电路4和控制电路5.数字均衡器2设置在AID转换器1和内插器3之间，并且根据来自合成器7的固定时钟CLK的定时对来自A / D转换器1的数字重放数据执行均衡处理。数字均衡器2的系数由控制电路5通过使用系数设定装置6根据来自定时恢复电路4的频率比信息4a来更新。因此，尽管进行均衡处理，但时钟提取能力增强由数字均衡器重放信号。

4. 发明申请

US20060044990A1 Phase error detecting circuit and synchronization clock extraction circuit 失效
标题翻译：相位误差检测电路和同步时钟提取电路
公开(公告)号：US20060044990A1
公开(公告)日：2006-03-02
申请号：US10533434
申请日：2004-06-11
申请人： Akira Kawabe , Kouji Okamoto
发明人： Akira Kawabe , Kouji Okamoto
IPC分类号： G11B7/00
CPC分类号： H03L7/091 , G11B20/10009 , G11B20/18 , H04L7/0334
摘要： In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generator 72 inputs, as a rising cross reference value S5, rising phase error data S3 calculated in a phase error calculator 71 to a rising cross detector 70a and inputs, as a falling cross reference value S6, falling phase error data S4 similarly calculated to a falling cross detector 70b. Each of the cross detectors 70a and 70b calculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) S5 or S6 and outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.
摘要翻译：在用于提取与再现数据同步的时钟的同步时钟提取电路中使用的相位误差检测电路中，交叉参考值发生器72输入作为上升交叉参考值S 5的上升相位误差数据S 3，将相位误差计算器71提供给上升交叉检测器70a，并将与下降交叉检测器70b类似地计算出的下降相位误差数据S 4输入作为下降交叉参考值S6。交叉检测器70a和70b中的每一个计算采样点的再现数据的值与输入的交叉参考值（交叉偏移值）S 5或S 6之间的差值，并输出上升或下降交叉检测信号当连续采样点的两个差值之一为负，另一个为正时。因此，捕获范围被扩大。

5. 发明授权

US06895348B2 Information playback apparatus with an unusual waveform circuit 失效
标题翻译：具有异常波形电路的信息播放装置
公开(公告)号：US06895348B2
公开(公告)日：2005-05-17
申请号：US10340273
申请日：2003-01-10
申请人： Akira Kawabe , Koichi Nagano
发明人： Akira Kawabe , Koichi Nagano
IPC分类号： G11B20/10 , G11B20/18 , G11B5/09
CPC分类号： G11B20/18
摘要： An unusual waveform detection circuit is a digital-type unusual waveform detection circuit that arbitrarily sets a threshold used for determining an unusual waveform and produces an unusual waveform determination signal by comparing an input signal with the threshold. In producing the unusual waveform determination signal, one of a configuration where a voltage at each of all sampling points is compared with a reference voltage and a configuration where a continuously changing gradient of signal waveform peaks is calculated and is compared with a reference gradient is selectively employed. The unusual waveform detection circuit can easily and accurately detect various unusual waveforms.
摘要翻译：异常波形检测电路是数字型异常波形检测电路，其任意设定用于确定异常波形的阈值，并通过将输入信号与阈值进行比较来产生异常波形判定信号。在产生异常波形确定信号时，将所有采样点中的每一个电压与参考电压进行比较的结构之一以及计算信号波形峰值的连续变化梯度并与参考梯度进行比较的配置选择性地雇用。异常波形检测电路可以方便，准确地检测各种异常波形。

6. 发明授权

US08154434B2 Pipelined A/D converter 有权
标题翻译：流水线A / D转换器
公开(公告)号：US08154434B2
公开(公告)日：2012-04-10
申请号：US13089673
申请日：2011-04-19
申请人： Akira Kawabe , Shinichi Ogita
发明人： Akira Kawabe , Shinichi Ogita
IPC分类号： H03M1/34
CPC分类号： H03M1/1019 , H03M1/168 , H03M1/44
摘要： Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation. Thereby, aliasing at decoding of the stage output is prevented, enabling an output range to be used effectively.
摘要翻译：多级顺序地将各个输入模拟信号转换成部分数字数据。每个阶段包括：部分A / D转换器; 部分D / A转换器; 加法器，用于对来自前一级的模拟信号和来自部分D / A转换器的输出进行加/减; 以及增益放大器，其放大加法器的输出并提供给下一级。流水线A / D转换器还包括：校正值相加单元，其将来自解码器单元的输出校正值相加; 校正值计算单元，其基于来自所述校正值相加单元的输出，计算所述输入/输出特性中的两点处的输出数据的中值与理想中值之间的误差，将所计算的值作为校正值并将其提供给校正值添加单元; 以及控制单元，其控制上述单元以执行校正操作。由此，能够防止在阶段输出的解码时的混叠，能够有效地使用输出范围。

7. 发明申请

US20110304366A1 PLL CIRCUIT 审中-公开
标题翻译： PLL电路
公开(公告)号：US20110304366A1
公开(公告)日：2011-12-15
申请号：US13014370
申请日：2011-01-26
申请人： Tadayuki Kanda , Akira Kawabe
发明人： Tadayuki Kanda , Akira Kawabe
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/095
摘要： A PLL circuit comprises a phase frequency detector configured to output a phase frequency difference signal with a pulse duration according to a phase difference and a frequency difference between a reference clock signal and a feedback clock signal according to an output clock signal; a charge pump circuit configured to output a charge pump current which is an output current according to the phase frequency difference signal and reduce a charge pump current amount in accordance with a charge pump current amount control signal for reducing the charge pump current amount stepwisely; and a lock detecting unit configured to detect whether or not the feedback clock signal is locked to the reference clock signal and output a lock detection signal when detecting a lock of the reference clock signal and the feedback clock signal
摘要翻译： PLL电路包括相位频率检测器，其被配置为根据输出时钟信号，根据相位差和参考时钟信号与反馈时钟信号之间的频率差输出具有脉冲持续时间的相位差信号; 电荷泵电路，被配置为输出根据所述相位差信号的作为输出电流的电荷泵电流，并根据用于逐步减小所述电荷泵电流量的电荷泵电流量控制信号减小电荷泵电流量; 以及锁定检测单元，被配置为检测反馈时钟信号是否被锁定到参考时钟信号，并且当检测到参考时钟信号和反馈时钟信号的锁定时输出锁定检测信号

8. 发明申请

US20080036637A1 Current addition type digital analog converter 失效
标题翻译：当前加法型数字模拟转换器
公开(公告)号：US20080036637A1
公开(公告)日：2008-02-14
申请号：US11889129
申请日：2007-08-09
申请人： Akira Kawabe , Akio Yokoyama
发明人： Akira Kawabe , Akio Yokoyama
IPC分类号： H03M1/66 , G05F1/02
CPC分类号： H03M1/002 , H03M1/745
摘要： A digital analog converter includes a current conversion section and a voltage conversion section. The current conversion section has a first output terminal and a second output terminal. The first output terminal outputs a first current and a second output terminal outputs a second current, the first current varying in value according to inputted digital data, the sum of the first current and the second current becoming a constant current. The voltage conversion section converts the first current to a corresponding first voltage and produces an offset voltage on the basis of the constant current and outputs the sum of the first voltage and the offset voltage as an output voltage.
摘要翻译：数字模拟转换器包括电流转换部分和电压转换部分。电流转换部分具有第一输出端和第二输出端。第一输出端子输出第一电流，第二输出端子输出第二电流，第一电流根据输入的数字数据变化值，第一电流和第二电流的和变为恒定电流。电压转换部将第一电流转换为对应的第一电压，并根据恒定电流产生偏移电压，并输出第一电压和偏移电压的和作为输出电压。

9. 发明授权

US08203474B2 Pipeline A/D converter 有权
标题翻译：管道A / D转换器
公开(公告)号：US08203474B2
公开(公告)日：2012-06-19
申请号：US12935387
申请日：2009-03-03
申请人： Shinichi Ogita , Akira Kawabe , Takayasu Kito
发明人： Shinichi Ogita , Akira Kawabe , Takayasu Kito
IPC分类号： H03M1/10
CPC分类号： H03M1/108 , H03M1/167 , H03M1/44
摘要： In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal. A test signal can be input with a small-scale configuration, without providing a test signal line separately from a line used for normal operation.
摘要翻译：在每个级中，从输入的模拟信号产生与一部分位对应的数字信号，基于数字信号由DA转换部分（7,8）产生模拟参考信号，并且在输入端产生余数运算模拟信号由余数运算部（9）进行。可以通过提供测试信号代替输入的模拟信号来进行测试。控制部（14a）在测试模式下进行控制，停止将输入的模拟信号提供给余数运算部，并基于数字信号停止DA转换部的基准电压选择，同时进行基于参考电压的选择在用于测试的DA转换控制信号上，从而为剩余操作部分提供由预定的参考电压组成的测试信号，代替输入的模拟信号和模拟参考信号。可以以小规模配置输入测试信号，而不将测试信号线与用于正常操作的线分开。

10. 发明申请

US20110193730A1 PIPELINED A/D CONVERTER 有权
标题翻译：管路A / D转换器
公开(公告)号：US20110193730A1
公开(公告)日：2011-08-11
申请号：US13089673
申请日：2011-04-19
申请人： Akira KAWABE , Shinichi OGITA
发明人： Akira KAWABE , Shinichi OGITA
IPC分类号： H03M1/00
CPC分类号： H03M1/1019 , H03M1/168 , H03M1/44
摘要： Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation. Thereby, aliasing at decoding of the stage output is prevented, enabling an output range to be used effectively.
摘要翻译：多级顺序地将各个输入模拟信号转换成部分数字数据。每个阶段包括：部分A / D转换器; 部分D / A转换器; 加法器，用于对来自前一级的模拟信号和来自部分D / A转换器的输出进行加/减; 以及增益放大器，其放大加法器的输出并提供给下一级。流水线A / D转换器还包括：校正值相加单元，其将来自解码器单元的输出校正值相加; 校正值计算单元，其基于来自所述校正值相加单元的输出，计算所述输入/输出特性中的两点处的输出数据的中值与理想中值之间的误差，将所计算的值作为校正值并将其提供给校正值添加单元; 以及控制单元，其控制上述单元以执行校正操作。由此，能够防止在阶段输出的解码时的混叠，能够有效地使用输出范围。

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