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1. 发明申请

US20110304366A1 PLL CIRCUIT 审中-公开
标题翻译： PLL电路
公开(公告)号：US20110304366A1
公开(公告)日：2011-12-15
申请号：US13014370
申请日：2011-01-26
申请人： Tadayuki Kanda , Akira Kawabe
发明人： Tadayuki Kanda , Akira Kawabe
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/095
摘要： A PLL circuit comprises a phase frequency detector configured to output a phase frequency difference signal with a pulse duration according to a phase difference and a frequency difference between a reference clock signal and a feedback clock signal according to an output clock signal; a charge pump circuit configured to output a charge pump current which is an output current according to the phase frequency difference signal and reduce a charge pump current amount in accordance with a charge pump current amount control signal for reducing the charge pump current amount stepwisely; and a lock detecting unit configured to detect whether or not the feedback clock signal is locked to the reference clock signal and output a lock detection signal when detecting a lock of the reference clock signal and the feedback clock signal
摘要翻译： PLL电路包括相位频率检测器，其被配置为根据输出时钟信号，根据相位差和参考时钟信号与反馈时钟信号之间的频率差输出具有脉冲持续时间的相位差信号; 电荷泵电路，被配置为输出根据所述相位差信号的作为输出电流的电荷泵电流，并根据用于逐步减小所述电荷泵电流量的电荷泵电流量控制信号减小电荷泵电流量; 以及锁定检测单元，被配置为检测反馈时钟信号是否被锁定到参考时钟信号，并且当检测到参考时钟信号和反馈时钟信号的锁定时输出锁定检测信号

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