会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Driving circuit for a microcomputer that enables sleep control using a
small-scale timer
    • 用于使用小型定时器进行睡眠控制的微型计算机的驱动电路
    • US5737588A
    • 1998-04-07
    • US499174
    • 1995-07-07
    • Kouichi MaedaHideaki IshiharaAkihiro Sasaki
    • Kouichi MaedaHideaki IshiharaAkihiro Sasaki
    • G06F1/04G06F1/32
    • G06F1/3237G06F1/3203Y02B60/1221
    • For a system which receives a sleep command to terminate the application of machine clock signals to a microprocessor and which clocks control execution time and stabilization time after the return from sleep control and resumes the supply of the machine clock signal, the clocking device for each of the time durations is implemented using a small-scale timing device. Following a sleep command from a microprocessor, sleep control, which terminates the operation of the main oscillator and the machine clock generation circuit that generates the machine clock signal based on the oscillation of the main oscillator, is started. Then, counting the oscillation signal from an RC oscillator used for clocking using an RC timer, the lapse time after starting sleep control is started and if the clocked time reaches a predetermined time, the main oscillator is reactivated. After reactivating the main oscillator, the RC timer is reset so that it begins to count the time thereafter starting from "0" and if the clocked time reaches the time needed for the oscillation of the main oscillator to stabilize, the machine clock generation circuit resumes its operations.
    • 对于接收休眠命令以终止对微处理器的机器时钟信号的应用的系统,以及在从睡眠控制返回之后控制执行时间和稳定时间的时钟,并且恢复提供机器时钟信号的时钟控制装置, 使用小规模定时装置实现持续时间。 在从微处理器执行睡眠命令之后,开始基于主振荡器的振荡而终止主振荡器和产生机器时钟信号的机器时钟产生电路的操作的睡眠控制。 然后,使用RC定时器对用于定时的RC振荡器进行振荡信号的计数,开始睡眠控制后的经过时间开始,如果时钟时间达到预定时间,则主振荡器被重新激活。 在重新激活主振荡器之后,RC定时器复位,使其开始计数其后从“0”开始的时间,如果时钟时间达到主振荡器稳定所需的时间,则机器时钟产生电路恢复 其业务。
    • 8. 发明申请
    • Electronic control apparatus
    • 电子控制装置
    • US20050251305A1
    • 2005-11-10
    • US10517123
    • 2003-05-28
    • Junkei SatoAkihiro Sasaki
    • Junkei SatoAkihiro Sasaki
    • G05B19/042G06F7/00G06F12/08
    • G05B19/042G05B2219/23306G05B2219/2637
    • The objective is to provide an electronic control apparatus capable of overwriting data in a nonvolatile memory, even during control operation. An ECU (10) includes a CPU (100), a flash EEPROM 101, and a calibration RAM (102). When calibration is performed, data in a calibration area of the flash EEPROM (101) is stored into the calibration RAM (102). A memory area of the calibration RAM (102) is overlapped over the calibration area to perform calibration. The data in the calibration area is written into the calibration RAM (102). When the calibration is completed, a super-user mode is entered in which the data stored in the calibration RAM (102) is written into the flash EEPROM (101) by use of a control register (113).
    • 目的是提供一种能够在非易失性存储器中重写数据的电子控制装置,即使在控制操作期间也是如此。 ECU(10)包括CPU(100),快闪EEPROM 101和校准RAM(102)。 当执行校准时,闪存EEPROM(101)的校准区域中的数据被存储到校准RAM(102)中。 校准RAM(102)的存储区域重叠在校准区域上以执行校准。 校准区域中的数据被写入校准RAM(102)。 当校准完成时,输入超级用户模式,通过使用控制寄存器(113)将存储在校准RAM(102)中的数据写入快闪EEPROM(101)。
    • 9. 发明授权
    • Microprocessor having built-in CRC section and method for performing CRC operations using the same
    • 具有内置CRC部分的微处理器和使用该部分执行CRC操作的方法
    • US06195779B1
    • 2001-02-27
    • US08499009
    • 1995-07-06
    • Kyouichi SuzukiHideaki IshiharaAkihiro SasakiNobutomo Takagi
    • Kyouichi SuzukiHideaki IshiharaAkihiro SasakiNobutomo Takagi
    • H03M1300
    • H03M13/09G06F11/10
    • To provide a microprocessor that can perform high-speed CRC code generation and can be implemented simply and at a low cost, a microprocessor has, at a part of a data input path to a shift circuit which is conventionally installed in an ALU of the microprocessor to execute shift commands, one bit of data that corresponds to the path, an exclusive OR circuit, which computes the exclusive OR of an uppermost bit of byte data and a bit data, is provided. For this circuit, a result according to a generating polynomial such as [X8+X4+X3+X2+1] is determined on the basis of the installation location of the exclusive OR circuit along the path, and by setting an initial value to the byte data, inputting one bit of the transmission data sequentially to the bit data and operating the shift circuit, a computed result for the CRC code is derived. Consequently, for the microprocessor, the CRC code can be generated at a high speed using the computation commands of the CRC code section. Corresponding techniques for error-checking of received data are also disclosed.
    • 为了提供可以执行高速CRC代码生成并且可以简单且低成本地实现的微处理器,微处理器在通常安装在微处理器的ALU中的移位电路的数据输入路径的一部分处 为了执行移位命令,对应于该路径的一位数据,提供计算字节数据的最高位和位数据的异或的异或电路。 对于该电路,根据诸如[X8 + X4 + X3 + X2 + 1]的生成多项式的结果是基于异或电路沿着路径的安装位置确定的,并且通过将初始值设置为 字节数据,将发送数据的一位顺序地输入到位数据并操作移位电路,导出CRC码的计算结果。 因此,对于微处理器,可以使用CRC码部分的计算命令以高速度生成CRC码。 还公开了用于接收数据的错误检查的相应技术。
    • 10. 发明授权
    • Data communication system and electronic control unit used therein
    • 数据通信系统及其中使用的电子控制单元
    • US06167057A
    • 2000-12-26
    • US26181
    • 1998-02-19
    • Tomohisa KishigamiAkihiro SasakiShigeru UeharaYasushi ShinojimaAkihiro Tanaka
    • Tomohisa KishigamiAkihiro SasakiShigeru UeharaYasushi ShinojimaAkihiro Tanaka
    • H04L1/00H04L12/40H04L12/413H04L29/06H04L29/08H04L3/12H04L3/16
    • H04L1/009H04L1/0007H04L1/0083H04L12/4135H04L29/06H04L69/324
    • In a data communication system in which many nodes are connected to a common data bus so that each node can communicate with other nodes, a data frame to be transmitted from a node to other nodes includes a message having a variable length interposed between a signal indicating the length of the message and a signal indicating the end of the message in the frame. The message and the signals are coded according to a coding rule such as NRZ, and a bit stuffing rule is applied to the signal indicating the length of the message and the message while another rule violating the bit stuffing rule is applied to the signal indicating the end of the message. When the message length is changed due to noise or other causes in the course of data transmission, the signal indicating the end of the message is clearly detected at a receiving end because it is coded according to a rule different from the rule applied to the message and other signals. Further, since the length of the message actually received at the receiving end can be compared with the signal indicating the length of the message, transmission error can be detected without fail.
    • 在其中许多节点连接到公共数据总线使得每个节点可以与其他节点通信的数据通信系统中,要从节点传送到其他节点的数据帧包括插入在指示 消息的长度和指示帧中消息结束的信号。 消息和信号根据诸如NRZ的编码规则进行编码,并且将位填充规则应用于指示消息和消息的长度的信号,而将违反位填充规则的另一规则应用于指示 消息结束。 当消息长度由于数据传输过程中的噪声或其他原因而改变时,在接收端清楚地检测出指示消息结束的信号,因为它根据与应用于消息的规则不同的规则进行编码 和其他信号。 此外,由于可以将在接收端实际接收的消息的长度与指示消息的长度的信号进行比较,所以可以毫无疑问地检测到传输错误。