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1. 发明授权

US5790603A Communication apparatus with collision detection and edge detection for transmitting and receiving data 失效
标题翻译：具有碰撞检测和边缘检测的通信装置，用于发送和接收数据
公开(公告)号：US5790603A
公开(公告)日：1998-08-04
申请号：US546847
申请日：1995-10-23
申请人： Kouichi Maeda , Hideaki Ishihara , Tengo Fujii , Akihiro Sasaki , Yasushi Kanda
发明人： Kouichi Maeda , Hideaki Ishihara , Tengo Fujii , Akihiro Sasaki , Yasushi Kanda
IPC分类号： G06F13/00 , H04L12/413 , H04L7/00
CPC分类号： H04L12/40013 , H04L12/413
摘要： A communication apparatus is used in a communication system, having a communication line, where an operation timing in each of the communication apparatus is coupled to the communication line and synchronized with the received signals in each of the communication apparatus. This communication apparatus comprises a signal-chip microprocessor having a central processing unit for executing main and interruption processing, a register storing data to be transmitted next, an output buffer for transmitting the transmission data, and an edge detector for detecting an edge in the communication line. The output buffer is directly responsive to an edge detection circuit, so that the transmission data can be immediately transmitted in response to the detection of an edge without a variable delay time caused by the operation condition which may be varied by the interruption processing or like.
摘要翻译：在具有通信线路的通信系统中使用通信装置，其中通信装置中的每一个中的操作定时与通信线路耦合并且与每个通信装置中的接收信号同步。该通信装置包括：信号芯片微处理器，具有用于执行主处理和中断处理的中央处理单元，存储要接下来要发送的数据的寄存器，用于发送传输数据的输出缓冲器，以及用于检测通信中边缘的边缘检测器线。输出缓冲器直接响应于边缘检测电路，从而响应于边缘的检测而可以立即发送传输数据，而不会由可能由于中断处理等而改变的操作条件引起可变延迟时间。

2. 发明授权

US5684838A Receiving device for sampling data bits at a preferred time 失效
标题翻译：在优选时间采样数据位的接收装置
公开(公告)号：US5684838A
公开(公告)日：1997-11-04
申请号：US542303
申请日：1995-10-12
申请人： Yasushi Kanda , Akihiro Sasaki , Nobutomo Takagi , Hideaki Ishihara , Kouichi Maeda , Tengo Fujii
发明人： Yasushi Kanda , Akihiro Sasaki , Nobutomo Takagi , Hideaki Ishihara , Kouichi Maeda , Tengo Fujii
IPC分类号： H04L1/00 , H04L7/027 , H04L7/033 , H04L25/03 , H04L25/40 , H04L7/00
CPC分类号： H04L7/033
摘要： In a receiving device, when a communication signal, which changes between low level and high level, is received via a filter circuit, an occurrence of an edge of the filtered received signal is monitored. Upon detection of the edge, a type of the edge, that is, whether the edge is a leading or trailing edge, is determined. Depending on the type of the edge, one of preset times prestored corresponding to types of the edges, is selected and starts to be measured. When the selected preset time elapses, the filtered received signal is sampled. With this arrangement, even when a filtering time of the filter circuit differs depending on a type of the edge of the communication signal, a constant sampling timing relative to the communication signal can be achieved irrespective of whether the detected edge is the leading or trailing edge.
摘要翻译：在接收装置中，当经由滤波器电路接收到在低电平和高电平之间变化的通信信号时，监视已滤波的接收信号的边沿的出现。在检测到边缘时，确定边缘的类型，即边缘是前缘还是后缘。根据边缘的类型，选择与预先存储的对应于边缘类型的预置时间之一，并开始测量。当所选择的预设时间过去时，滤波的接收信号被采样。利用这种布置，即使当滤波器电路的滤波时间根据通信信号的边缘的类型而不同时，可以实现相对于通信信号的恒定采样定时，而不管所检测的边沿是前沿还是后沿。

3. 发明授权

US5737588A Driving circuit for a microcomputer that enables sleep control using a small-scale timer 失效
标题翻译：用于使用小型定时器进行睡眠控制的微型计算机的驱动电路
公开(公告)号：US5737588A
公开(公告)日：1998-04-07
申请号：US499174
申请日：1995-07-07
申请人： Kouichi Maeda , Hideaki Ishihara , Akihiro Sasaki
发明人： Kouichi Maeda , Hideaki Ishihara , Akihiro Sasaki
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , Y02B60/1221
摘要： For a system which receives a sleep command to terminate the application of machine clock signals to a microprocessor and which clocks control execution time and stabilization time after the return from sleep control and resumes the supply of the machine clock signal, the clocking device for each of the time durations is implemented using a small-scale timing device. Following a sleep command from a microprocessor, sleep control, which terminates the operation of the main oscillator and the machine clock generation circuit that generates the machine clock signal based on the oscillation of the main oscillator, is started. Then, counting the oscillation signal from an RC oscillator used for clocking using an RC timer, the lapse time after starting sleep control is started and if the clocked time reaches a predetermined time, the main oscillator is reactivated. After reactivating the main oscillator, the RC timer is reset so that it begins to count the time thereafter starting from "0" and if the clocked time reaches the time needed for the oscillation of the main oscillator to stabilize, the machine clock generation circuit resumes its operations.
摘要翻译：对于接收休眠命令以终止对微处理器的机器时钟信号的应用的系统，以及在从睡眠控制返回之后控制执行时间和稳定时间的时钟，并且恢复提供机器时钟信号的时钟控制装置，使用小规模定时装置实现持续时间。在从微处理器执行睡眠命令之后，开始基于主振荡器的振荡而终止主振荡器和产生机器时钟信号的机器时钟产生电路的操作的睡眠控制。然后，使用RC定时器对用于定时的RC振荡器进行振荡信号的计数，开始睡眠控制后的经过时间开始，如果时钟时间达到预定时间，则主振荡器被重新激活。在重新激活主振荡器之后，RC定时器复位，使其开始计数其后从“0”开始的时间，如果时钟时间达到主振荡器稳定所需的时间，则机器时钟产生电路恢复其业务。

4. 发明授权

US06304957B1 Multitask processing unit 失效
标题翻译：多任务处理单元
公开(公告)号：US06304957B1
公开(公告)日：2001-10-16
申请号：US08202181
申请日：1994-02-25
申请人： Hideaki Ishihara , Kouichi Maeda
发明人： Hideaki Ishihara , Kouichi Maeda
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851
摘要： The microcomputer shall be offered which has realized more simplified peripheral circuits and more reduced price, besides being provided with the functions of timer, runaway monitor and backup logic. To that effect, the address register and the register are installed which have two areas each in correspondence with two tasks (CPU0 and CPU1) to perform a pipeline processing of the two tasks in parallel and in time division by changing over alternately the two areas of the address register and the register by means of task switching signal. Then, while composing one task (L-task) with a fix-looped program for which a branch instruction is prohibited, the L-task is embedded with a routine to execute a runaway monitor and a timer operation for the other task (A-task). Furthermore, in case where anything abnormal is detected by L-task about the processing of A-task and it is reset, the L-task will execute a backup sequence to obtain a failsafe of the system.
摘要翻译：提供微型计算机，除了提供定时器，失控监视器和备用逻辑的功能外，还实现了更简化的外围电路，降低了价格。为此，安装了地址寄存器和寄存器，它们具有两个对应于两个任务（CPU0和CPU1）的两个区域，以并行地并且通过分时地改变两个任务的两个区域来执行两个任务的流水线处理地址寄存器和寄存器通过任务切换信号。然后，当使用禁止分支指令的固定循环程序来组合一个任务（L任务）时，L任务被嵌入一个例程以执行失控监视器和另一任务的定时器操作（A- 任务）。此外，如果L任务检测到任何关于A任务的处理的任何异常并且被复位，则L任务将执行备份序列以获得系统的故障保护。

5. 发明授权

US6131073A Electronic circuit with an operating characteristic correcting function 失效
标题翻译：具有操作特性校正功能的电子电路
公开(公告)号：US6131073A
公开(公告)日：2000-10-10
申请号：US870732
申请日：1997-06-06
申请人： Yoshimitsu Honda , Hideaki Ishihara , Haruyasu Sakishita , Kouichi Maeda
发明人： Yoshimitsu Honda , Hideaki Ishihara , Haruyasu Sakishita , Kouichi Maeda
IPC分类号： H01L27/04 , G01R1/44 , G05F1/56 , H01L21/822 , H03K19/003
CPC分类号： G01R1/44
摘要： A power voltage of a power source circuit is produced by amplifying a threshold voltage difference of an operational amplifier by an amplification factor corresponding to a dividing ratio of a resistance dividing circuit. The power source circuit is integrated on a CMOS substrate together with a computer block. A plurality of analog switches are associated with the resistance dividing circuit to stabilize the power voltage of the power source circuit. One of these switches is selectively closed to change the dividing ratio of the resistance dividing circuit in accordance with actuation data stored in a control register.
摘要翻译：电源电路的电源电压通过将运算放大器的阈值电压差放大到与电阻分割电路的分频比相对应的放大系数来产生。电源电路与计算机块一起集成在CMOS衬底上。多个模拟开关与电阻划分电路相关联，以稳定电源电路的电源电压。这些开关中的一个选择性地闭合，以根据存储在控制寄存器中的致动数据改变电阻分割电路的分压比。

6. 发明授权

US06581119B1 Interrupt controller and a microcomputer incorporating this controller 失效
标题翻译：中断控制器和包含该控制器的微型计算机
公开(公告)号：US06581119B1
公开(公告)日：2003-06-17
申请号：US09598321
申请日：2000-06-21
申请人： Kouichi Maeda , Hideaki Ishihara , Sinichi Noda
发明人： Kouichi Maeda , Hideaki Ishihara , Sinichi Noda
IPC分类号： G06F1324
CPC分类号： G06F13/26
摘要： To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.
摘要翻译：为了减小能够执行多个中断的微型计算机的CPU的电路规模，中断控制器包括中断屏蔽级别寄存器。 CPU临时将处理数据传输或堆栈到RAM中。处理数据包括当前在CPU中运行的中断处理的PSR（即，系统寄存器）值和PC（即，程序计数器）值。同时，CPU向中断控制器发送堆栈信号“STK”。响应于堆栈信号“STK”，中断控制器将存储在寄存器中的中断屏蔽电平临时传送到RAM中。当CPU重新启动暂停的中断处理时，CPU在CPU产生返回信号“RTN”时从RAM读取PSR值和PC值。响应于返回信号“RTN”，中断屏蔽电平从RAM返回到寄存器。

7. 发明授权

US06195779B1 Microprocessor having built-in CRC section and method for performing CRC operations using the same 失效
标题翻译：具有内置CRC部分的微处理器和使用该部分执行CRC操作的方法
公开(公告)号：US06195779B1
公开(公告)日：2001-02-27
申请号：US08499009
申请日：1995-07-06
申请人： Kyouichi Suzuki , Hideaki Ishihara , Akihiro Sasaki , Nobutomo Takagi
发明人： Kyouichi Suzuki , Hideaki Ishihara , Akihiro Sasaki , Nobutomo Takagi
IPC分类号： H03M1300
CPC分类号： H03M13/09 , G06F11/10
摘要： To provide a microprocessor that can perform high-speed CRC code generation and can be implemented simply and at a low cost, a microprocessor has, at a part of a data input path to a shift circuit which is conventionally installed in an ALU of the microprocessor to execute shift commands, one bit of data that corresponds to the path, an exclusive OR circuit, which computes the exclusive OR of an uppermost bit of byte data and a bit data, is provided. For this circuit, a result according to a generating polynomial such as [X8+X4+X3+X2+1] is determined on the basis of the installation location of the exclusive OR circuit along the path, and by setting an initial value to the byte data, inputting one bit of the transmission data sequentially to the bit data and operating the shift circuit, a computed result for the CRC code is derived. Consequently, for the microprocessor, the CRC code can be generated at a high speed using the computation commands of the CRC code section. Corresponding techniques for error-checking of received data are also disclosed.
摘要翻译：为了提供可以执行高速CRC代码生成并且可以简单且低成本地实现的微处理器，微处理器在通常安装在微处理器的ALU中的移位电路的数据输入路径的一部分处为了执行移位命令，对应于该路径的一位数据，提供计算字节数据的最高位和位数据的异或的异或电路。对于该电路，根据诸如[X8 + X4 + X3 + X2 + 1]的生成多项式的结果是基于异或电路沿着路径的安装位置确定的，并且通过将初始值设置为字节数据，将发送数据的一位顺序地输入到位数据并操作移位电路，导出CRC码的计算结果。因此，对于微处理器，可以使用CRC码部分的计算命令以高速度生成CRC码。还公开了用于接收数据的错误检查的相应技术。

8. 发明授权

US09116213B2 Secondary battery state detecting device and secondary battery state detecting method 有权
标题翻译：二次电池状态检测装置和二次电池状态检测方法
公开(公告)号：US09116213B2
公开(公告)日：2015-08-25
申请号：US13847985
申请日：2013-03-20
申请人： Etsuzo Sato , Hideaki Ishihara , Fukuda Kazumi , Naoki Ishiyone
发明人： Etsuzo Sato , Hideaki Ishihara , Fukuda Kazumi , Naoki Ishiyone
IPC分类号： G01R31/36
CPC分类号： G01R31/3606 , G01R19/04 , G01R31/3662 , G01R31/3693
摘要： A current detecting unit (current sensor 12) detecting a current value of a current flowing in a secondary battery 14; an extreme value detecting unit (CPU 10a) detecting a first extreme value of a current after an inrush current flows from the secondary battery to a starter motor after electricity to the starter motor is turned on based on the current value; an inflection point detecting unit (CPU 10a) detecting a first inflection point of the current after the inrush current flows based on a variation of the current value per a predetermined time; and a calculation unit (CPU 10a) selecting the inflection point when timings when the extreme value and the inflection point are detected are separated for a predetermined time or more, and selecting either one of the extreme value or the inflection point in the other cases to set as a starting current, and calculating a starting voltage from the starting current, an internal resistance of the secondary battery, and a voltage before starting being a voltage of the secondary battery before the electricity to the starter motor is turned on, are included.
摘要翻译：电流检测单元（电流传感器12），检测在二次电池14中流动的电流的电流值; 基于当前值，接通电流后，检测从二次电池流入起动电动机的起动电流之后的电流的第一极值的极值检测部（CPU10a）。基于每个预定时间的当前值的变化，检测涌流之后的电流的第一拐点的拐点检测单元（CPU 10a）; 以及当检测到极值和拐点时的定时时选择拐点的计算单元（CPU 10a）分离预定时间或更长时间，并且在其他情况下选择极值或拐点中的任一个，设定为启动电流，并且计算来自起动电流的起动电压，二次电池的内部电阻以及在启动电动机之前的二次电池的开始电压之前的电压被接通。

9. 发明授权

US09030165B2 Operating machine 有权
标题翻译：操作机
公开(公告)号：US09030165B2
公开(公告)日：2015-05-12
申请号：US13614058
申请日：2012-09-13
申请人： Hiroaki Kawai , Koichi Shimomura , Hideaki Ishihara , Shintaro Sasai
发明人： Hiroaki Kawai , Koichi Shimomura , Hideaki Ishihara , Shintaro Sasai
IPC分类号： H02J7/00 , H02J7/14 , H02J7/04 , B60L11/18 , B60R16/033
CPC分类号： H02J7/041 , B60L11/1818 , B60R16/033 , H02J7/044 , H02J7/045 , H02J7/1446 , Y02T10/92
摘要： An operating machine includes: a charging time estimation unit that estimates a first estimated charging time required to restore a capacity of a first battery from a first estimated residual capacity to a target capacity value of the first battery and a second estimated charging time required to restore a capacity of a second battery from a second estimated residual capacity to a target capacity value of the second battery; a capacity management implementation unit that implements capacity management on the first battery and the second battery such that the first battery is charged for the first estimated charging time and the second battery is charged for the second estimated charging time; and a discharge amount limitation unit for limiting a discharge amount of the second battery during an idling stop so that a residual capacity of the second battery after discharge is maintained at or above a set value.
摘要翻译：操作机包括：充电时间估计单元，其估计将第一电池的容量从第一估计剩余容量恢复到第一电池的目标容量值所需的第一估计充电时间，以及恢复所需的第二估计充电时间从第二估计剩余容量到第二电池的目标容量值的第二电池的容量; 容量管理执行单元，其对所述第一电池和所述第二电池进行容量管理，使得所述第一电池对于所述第一估计充电时间进行充电，并且所述第二电池对所述第二估计充电时间进行充电; 以及排出量限制单元，用于在怠速停止期间限制第二电池的排出量，使得排出后的第二电池的剩余容量保持在设定值以上。

10. 发明申请

US20140153655A1 VEHICULAR POWER LINE COMMUNICATION SYSTEM AND TRANSMITTER 有权
标题翻译：电力线通信系统和发射机
公开(公告)号：US20140153655A1
公开(公告)日：2014-06-05
申请号：US14125758
申请日：2012-07-18
申请人： Taiji Abe , Akira Takaoka , Yuukou Murase , Hideaki Ishihara
发明人： Taiji Abe , Akira Takaoka , Yuukou Murase , Hideaki Ishihara
IPC分类号： H04B3/54
CPC分类号： H04B3/54 , H04B3/56 , H04B5/0018 , H04B2203/5416 , H04B2203/5445 , H04B2203/5483
摘要： An opening area between twisted portions of a pair of twisted wires is arranged to be opposite to an opening area of an aperture antenna of each of communication apparatuses. Thus, the use of the pair of twisted wires permits division of electric power among the communication apparatuses and also communication of signals. In particular, among the opening areas between the twisted portions of the pair of twisted wires, only an opening area, which is in between the twisted portion and the twisted portion and is opposite to the aperture antenna, is formed to be larger than a different opening area. This provides a vehicular power line communication system and a transmitter in the system; the system strengthens electromagnetic induction connection between the transmitter and the receiver to permit power line communication.
摘要翻译：一对扭绞线的扭转部分之间的开口区域布置成与每个通信设备的孔径天线的开口区域相对。因此，使用这对双绞线可以在通信装置之间进行电力分配，也可以进行信号的通信。特别地，在一对扭绞线的扭转部分之间的开口区域中，仅在扭转部分和扭转部分之间并且与孔径天线相对的开口区域形成为大于不同的开放区域。这提供了系统中的车辆电力线通信系统和发射机; 该系统加强了发射机和接收机之间的电磁感应连接，以实现电力线通信。

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