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1. 发明授权

US06195779B1 Microprocessor having built-in CRC section and method for performing CRC operations using the same 失效
标题翻译：具有内置CRC部分的微处理器和使用该部分执行CRC操作的方法
公开(公告)号：US06195779B1
公开(公告)日：2001-02-27
申请号：US08499009
申请日：1995-07-06
申请人： Kyouichi Suzuki , Hideaki Ishihara , Akihiro Sasaki , Nobutomo Takagi
发明人： Kyouichi Suzuki , Hideaki Ishihara , Akihiro Sasaki , Nobutomo Takagi
IPC分类号： H03M1300
CPC分类号： H03M13/09 , G06F11/10
摘要： To provide a microprocessor that can perform high-speed CRC code generation and can be implemented simply and at a low cost, a microprocessor has, at a part of a data input path to a shift circuit which is conventionally installed in an ALU of the microprocessor to execute shift commands, one bit of data that corresponds to the path, an exclusive OR circuit, which computes the exclusive OR of an uppermost bit of byte data and a bit data, is provided. For this circuit, a result according to a generating polynomial such as [X8+X4+X3+X2+1] is determined on the basis of the installation location of the exclusive OR circuit along the path, and by setting an initial value to the byte data, inputting one bit of the transmission data sequentially to the bit data and operating the shift circuit, a computed result for the CRC code is derived. Consequently, for the microprocessor, the CRC code can be generated at a high speed using the computation commands of the CRC code section. Corresponding techniques for error-checking of received data are also disclosed.
摘要翻译：为了提供可以执行高速CRC代码生成并且可以简单且低成本地实现的微处理器，微处理器在通常安装在微处理器的ALU中的移位电路的数据输入路径的一部分处为了执行移位命令，对应于该路径的一位数据，提供计算字节数据的最高位和位数据的异或的异或电路。对于该电路，根据诸如[X8 + X4 + X3 + X2 + 1]的生成多项式的结果是基于异或电路沿着路径的安装位置确定的，并且通过将初始值设置为字节数据，将发送数据的一位顺序地输入到位数据并操作移位电路，导出CRC码的计算结果。因此，对于微处理器，可以使用CRC码部分的计算命令以高速度生成CRC码。还公开了用于接收数据的错误检查的相应技术。

2. 发明授权

US08700956B2 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US08700956B2
公开(公告)日：2014-04-15
申请号：US13305133
申请日：2011-11-28
申请人： Yuuki Asada , Naoki Ito , Kyouichi Suzuki , Norio Fujimori
发明人： Yuuki Asada , Naoki Ito , Kyouichi Suzuki , Norio Fujimori
IPC分类号： G06F11/00
CPC分类号： G06F11/3656 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： A debug circuit of a microcomputer, providing an on-chip debug function, is provided as a measurement permission circuit for outputting a measurement permission signal to a timer that measures, as a measurement object, a time period between two events in a program execution period of the CPU, according to a user-specified condition. The measurement permission circuit includes an interrupt level register for setting an interrupt level that either permits or prohibits a time measurement operation of the timer, and a comparator for determining by comparison a high-low relationship between an interrupt level of an interrupt process executed by the CPU and an interrupt level set in the interrupt level register, and a determination result of the comparator is specified as the measurement permission signal.
摘要翻译：提供了提供片上调试功能的微型计算机的调试电路作为测量许可电路，用于向定时器输出测量许可信号，该定时器作为测量对象测量程序执行期间的两个事件之间的时间段的CPU，根据用户指定的条件。测量许可电路包括用于设置允许或禁止定时器的时间测量操作的中断电平的中断电平寄存器，以及用于通过比较确定由中断处理执行的中断处理的中断电平之间的高低关系的比较器 CPU和在中断级别寄存器中设置的中断级别，并将比较器的确定结果指定为测量许可信号。

3. 发明申请

US20080140920A1 Microcomputer for flash memory rewriting 有权
标题翻译：微机用于闪存重写
公开(公告)号：US20080140920A1
公开(公告)日：2008-06-12
申请号：US12000001
申请日：2007-12-06
申请人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
发明人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.
摘要翻译：提供一种微计算机和方法，其能够在重写非易失性存储器失败时重新启动重写程序，而不需要使用外部端子改变模式。微型计算机的CPU执行重写程序来清除闪存的FLASH状态0并重写其中的所有区域。 CPU最终将重写完成代码写入FLASH状态0。 CPU执行确定程序以读取闪存的FLASH状态0。当读取数据与重写完成代码不匹配时，CPU读取ID状态信息。当数据与ID状态信息匹配时，CPU重新执行重写程序。

4. 发明授权

US06531017B1 Color image-forming method and transfer sheet used for the method 失效
标题翻译：用于该方法的彩色成像方法和转印纸
公开(公告)号：US06531017B1
公开(公告)日：2003-03-11
申请号：US09473399
申请日：1999-12-28
申请人： Takuto Fukui , Toshiyuki Yamane , Kyouichi Suzuki , Hideki Suematsu
发明人： Takuto Fukui , Toshiyuki Yamane , Kyouichi Suzuki , Hideki Suematsu
IPC分类号： B41M530
CPC分类号： B41M5/385 , B41M5/345 , B41M5/38264 , B41M5/395 , B41M5/426 , B41M5/44
摘要： A color image-forming method, comprising the steps of: using a transfer sheet comprising a foundation, a release layer and a colored ink layer stacked in this order on one side of the foundation wherein the release layer is capable of being fused or softened by heat at the time of a thermal transferring process and the colored ink layer is incapable of being softened by heat at the time of the thermal transferring process; and an image receiving body having at least a surface layer capable of being fused or softened by heat at the time of the thermal transferring process, superposing the colored ink layer of the transfer sheet onto the image receiving body and heating the transfer sheet/image receiving body from the transfer sheet side to form a color image on the image receiving body.
摘要翻译：一种彩色图像形成方法，包括以下步骤：使用转印片，其中所述转印片包括基底，释放层和彩色墨层，所述基底，释放层和彩色墨层依次堆叠在所述基底的一侧上，其中所述剥离层能够被所述剥离层熔融或软化在热转印过程中的热量和着色油墨层在热转印过程中不能被热软化; 以及图像接收体，其具有在热转印过程中至少具有能够通过热熔融或软化的表面层，将转印片的着色墨层叠加到图像接收体上并加热转印片/图像接收从转印纸侧进行彩色图像形成在图像接收体上。

5. 发明申请

US20060218340A1 Data validity determining method for flash EEPROM and electronic control system 审中-公开
标题翻译：闪存EEPROM和电子控制系统的数据有效性确定方法
公开(公告)号：US20060218340A1
公开(公告)日：2006-09-28
申请号：US11384822
申请日：2006-03-21
申请人： Yoichi Fujita , Kyouichi Suzuki , Chihiro Tomimatsu
发明人： Yoichi Fujita , Kyouichi Suzuki , Chihiro Tomimatsu
IPC分类号： G06F12/00
CPC分类号： G06F11/073 , G06F11/0763
摘要： In an electronic control system, it is determined whether leading end identification information in a data verification space of a flash EEPROM of an electronic control unit is an expected value. When it is yes, it is then determined whether terminal identification information in the data verification space is the expected value. Then, when it is yes, it is determined whether the leading end identification information and the trailing end identification information are identical to each other. When it is yes, it is determined that data between the leading end identification information and the trailing end identification information is valid. Otherwise, it is determined that the data is invalid.
摘要翻译：在电子控制系统中，确定电子控制单元的快闪EEPROM的数据验证空间中的前端识别信息是否为预期值。当为是时，确定数据验证空间中的终端识别信息是否为期望值。然后，当为是时，确定前端识别信息和后端识别信息是否相同。当为是时，确定前端识别信息和尾端识别信息之间的数据是有效的。否则，确定数据无效。

6. 发明授权

US07934050B2 Microcomputer for flash memory rewriting 有权
标题翻译：微机用于闪存重写
公开(公告)号：US07934050B2
公开(公告)日：2011-04-26
申请号：US12000001
申请日：2007-12-06
申请人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
发明人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
IPC分类号： G06F13/00
CPC分类号： G06F12/0246
摘要： A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.
摘要翻译：提供一种微计算机和方法，其能够在重写非易失性存储器失败时重新启动重写程序，而不需要使用外部端子改变模式。微型计算机的CPU执行重写程序来清除闪存的FLASH状态0并重写其中的所有区域。 CPU最终将重写完成代码写入FLASH状态0. CPU执行确定程序以读取闪存的FLASH状态0。当读取数据与重写完成代码不匹配时，CPU读取ID状态信息。当数据与ID状态信息匹配时，CPU重新执行重写程序。

7. 发明申请

US20120137176A1 MICROCOMPUTER 有权
公开(公告)号：US20120137176A1
公开(公告)日：2012-05-31
申请号：US13305133
申请日：2011-11-28
申请人： Yuuki Asada , Naoki Ito , Kyouichi Suzuki , Norio Fujimori
发明人： Yuuki Asada , Naoki Ito , Kyouichi Suzuki , Norio Fujimori
IPC分类号： G06F11/36
CPC分类号： G06F11/3656 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： A debug circuit of a microcomputer, providing an on-chip debug function, is provided as a measurement permission circuit for outputting a measurement permission signal to a timer that measures, as a measurement object, a time period between two events in a program execution period of the CPU, according to a user-specified condition. The measurement permission circuit includes an interrupt level register for setting an interrupt level that either permits or prohibits a time measurement operation of the timer, and a comparator for determining by comparison a high-low relationship between an interrupt level of an interrupt process executed by the CPU and an interrupt level set in the interrupt level register, and a determination result of the comparator is specified as the measurement permission signal.
摘要翻译：提供了提供片上调试功能的微型计算机的调试电路作为测量许可电路，用于向定时器输出测量许可信号，该定时器作为测量对象测量程序执行期间的两个事件之间的时间段的CPU，根据用户指定的条件。测量许可电路包括用于设置允许或禁止定时器的时间测量操作的中断电平的中断电平寄存器，以及用于通过比较确定由中断处理执行的中断处理的中断电平之间的高低关系的比较器 CPU和在中断级别寄存器中设置的中断级别，并将比较器的确定结果指定为测量许可信号。

8. 发明授权

US07421384B2 Semiconductor integrated circuit device and microcomputer development supporting device 失效
标题翻译：半导体集成电路器件和微机开发支持器件
公开(公告)号：US07421384B2
公开(公告)日：2008-09-02
申请号：US11000902
申请日：2004-12-02
申请人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
发明人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
IPC分类号： G06F9/455 , G06F11/00 , G06F15/00 , G06F15/76 , G06F19/00 , G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14
CPC分类号： G06F11/261
摘要： During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.
摘要翻译：在软件开发过程中，使用一个多芯片模块，将一个目标芯片和一个开发芯片封装在一个封装中。开发芯片的CPU从芯片中的闪速存储器中获取指令以执行它们，并访问芯片中的RAM和外围电路。对于仅在目标芯片中存在的电机控制电路，CPU通过串行通信访问它们。当单片机单独运行时，其CPU将开关电路切换到JTAG接口侧，以通过内部串行通信来驱动电机控制电路。

9. 发明授权

US07162622B2 Microcomputer for apparatus control and vehicle-mounted electronic control unit incorporating microcomputer 有权
标题翻译：微机用于装置控制和车载电子控制单元结合微型计算机
公开(公告)号：US07162622B2
公开(公告)日：2007-01-09
申请号：US10367731
申请日：2003-02-17
申请人： Katsurou Sekiya , Hideaki Ishihara , Kyouichi Suzuki , Masahiro Kamiya
发明人： Katsurou Sekiya , Hideaki Ishihara , Kyouichi Suzuki , Masahiro Kamiya
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F9/4403
摘要： A microcomputer which is to be utilized in a condition of being built into an apparatus such as a vehicle ECU, includes a ROM having stored therein a program which is prepared by a user and a boot ROM which stores an initialization program for performing at least essential initialization processing which is required for all application programs that will be executed by the microcomputer. The need for the user to generate program contents relating to such initialization processing is thereby eliminated, while increased reliability of operation of the microcomputer is achieved. In addition, it is possible for user-specified initialization data to be read out from a user program and utilized in a part of the initialization processing of the initialization program.
摘要翻译：在车辆ECU等装置内置的微型计算机中，包括存储有由用户准备的程序的ROM和存储用于至少执行至少必要的初始化程序的引导ROM 由微型计算机执行的所有应用程序所需的初始化处理。从而消除了用户生成与这种初始化处理相关的节目内容的需要，同时实现了微型计算机的操作的可靠性的提高。此外，可以从用户程序读出用户指定的初始化数据，并在初始化程序的初始化处理的一部分中使用用户指定的初始化数据。

10. 发明申请

US20050125214A1 Semiconductor integrated circuit device and microcomputer development supporting device 失效
标题翻译：半导体集成电路器件和微机开发支持器件
公开(公告)号：US20050125214A1
公开(公告)日：2005-06-09
申请号：US11000902
申请日：2004-12-02
申请人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
发明人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
IPC分类号： G06F11/28 , G06F9/44 , G06F9/455 , G06F11/22 , G06F11/26 , G06F15/78
CPC分类号： G06F11/261
摘要： During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.
摘要翻译：在软件开发过程中，使用一个多芯片模块，将一个目标芯片和一个开发芯片封装在一个封装中。开发芯片的CPU从芯片中的闪速存储器中获取指令以执行它们，并访问芯片中的RAM和外围电路。对于仅在目标芯片中存在的电机控制电路，CPU通过串行通信访问它们。当单片机单独运行时，其CPU将开关电路切换到JTAG接口侧，以通过内部串行通信来驱动电机控制电路。

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