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1. 发明授权

US08341362B2 System, method and apparatus for memory with embedded associative section for computations 有权
标题翻译：用于计算的嵌入式联想部分的存储器的系统，方法和装置
公开(公告)号：US08341362B2
公开(公告)日：2012-12-25
申请号：US12650604
申请日：2009-12-31
申请人： Avidan Akerib , Eli Ehrman , Moshe Meyassed , Oren Agam
发明人： Avidan Akerib , Eli Ehrman , Moshe Meyassed , Oren Agam
IPC分类号： G06F13/00 , G06F13/28 , G09G5/36
CPC分类号： G11C7/1006 , G09G5/06 , G09G5/393
摘要： A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.
摘要翻译：一种用于数据处理的系统和方法，所述方法包括：以行方式将输入数据字存储在包括以行和列排列的多个存储单元的存储器中; 以及通过执行移位操作和关联操作的顺序来转置多个数据字; 其中关联操作包括将多个相关联存储器单元并行至少一个比较; 并将转置的数据字存储在存储器中。

2. 发明授权

US07965564B2 Processor arrays made of standard memory cells 有权
标题翻译：处理器阵列由标准存储单元组成
公开(公告)号：US07965564B2
公开(公告)日：2011-06-21
申请号：US12211919
申请日：2008-09-17
申请人： Yoav Lavi , Eli Ehrman , Avidan Akerib
发明人： Yoav Lavi , Eli Ehrman , Avidan Akerib
IPC分类号： G11C7/22
CPC分类号： G11C7/1006 , G11C7/02 , G11C11/412 , G11C15/04 , G11C15/043
摘要： Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs).
摘要翻译：使用标准存储器电路来执行存储在存储器中的数据与引入到存储器中的数据之间的积和积函数。产品总和功能以与标准存储器读取操作基本类似的方式执行。存储器电路是标准或略微修改的SRAM和DRAM单元，或计算存储器阵列（CAM）。

3. 发明申请

US20120246401A1 IN-MEMORY PROCESSOR 审中-公开
标题翻译：内存处理器
公开(公告)号：US20120246401A1
公开(公告)日：2012-09-27
申请号：US13502783
申请日：2010-10-21
申请人： Oren Agam , Moshe Meyassed , Yukio Fukuzo
发明人： Oren Agam , Moshe Meyassed , Yukio Fukuzo
IPC分类号： G06F12/00
CPC分类号： G11C7/1006
摘要： A memory device includes at least two memory banks storing data and an internal processor. The at least two memory banks are accessible by a host processor. The internal processor receives a timeslot from the host processor and processes a portion of the data from an indicated one of the at least two banks of the memory array during the timeslot while the remaining banks are available to the host processor during the timeslot. A method of operating a memory device having banks storing data includes a host processor issuing per bank timeslots to an internal processor of a memory device, the internal processor operating on an indicated bank of the memory device during the timeslot and the host processor not accessing the indicated bank during the timeslot.
摘要翻译：存储器件包括至少两个存储数据的存储体和内部处理器。至少两个存储体可由主处理器访问。内部处理器从主机处理器接收时隙，并且在时隙期间处理来自存储器阵列的至少两个存储体组中指定的一个的数据的一部分，而在时隙期间剩余的存储体可用于主机处理器。一种操作具有存储数据的存储器的存储器件的方法包括：主处理器，每个存储体时隙向存储器件的内部处理器发出，所述内部处理器在时隙期间在存储器件的指示库上操作，并且主机处理器不访问存储器在时间段内指定银行。

4. 发明申请

US20090254697A1 MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS 审中-公开
标题翻译：用于计算的嵌入式相关部分的内存
公开(公告)号：US20090254697A1
公开(公告)日：2009-10-08
申请号：US12119197
申请日：2008-05-12
申请人： Avidan Akerib , Eli Ehrman , Yoav Lavi , Moshe Meyassed
发明人： Avidan Akerib , Eli Ehrman , Yoav Lavi , Moshe Meyassed
IPC分类号： G06F12/00
CPC分类号： G11C7/1006
摘要： An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
摘要翻译：集成电路器件包括半导体衬底和随机存取存储器（RAM）单元阵列，其被布置在第一列中的衬底上，并被配置为存储数据。设备中的计算部分包括相关存储器单元，其被布置在第二列中的衬底上，其与RAM单元的相应的第一列对齐并且与相应的第一列通信，以便从阵列接收数据并且对数据执行关联计算。

5. 发明申请

US20120243284A1 USING STORAGE CELLS TO PERFORM COMPUTATION 有权
标题翻译：使用储存细胞进行计算
公开(公告)号：US20120243284A1
公开(公告)日：2012-09-27
申请号：US13437955
申请日：2012-04-03
申请人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
发明人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
IPC分类号： G11C15/00
CPC分类号： G11C29/34 , G11C15/043
摘要： A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.
摘要翻译：内容可寻址存储器（CAM）单元没有任何单元内比较器电路。 CAM单元包括存储器阵列，多行解码器，控制器和输出单元。存储器阵列具有排列成数据行和补码行的存储单元。多行解码器一次激活多于一行存储器阵列，并且控制器向多行解码器指示作为要匹配的输入模式的函数来激活数据行或补码行。输出单元指示哪些列生成信号，列与模式匹配。

6. 发明申请

US20120243283A1 USING STORAGE CELLS TO PERFORM COMPUTATION 有权
标题翻译：使用储存细胞进行计算
公开(公告)号：US20120243283A1
公开(公告)日：2012-09-27
申请号：US13437956
申请日：2012-04-03
申请人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
发明人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
IPC分类号： G11C15/00
CPC分类号： G11C29/34 , G11C15/043
摘要： A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells.
摘要翻译：一种方法包括激活至少两行纯存储器单元并读取激活的存储器单元的至少一列，该读取产生存储在激活的存储单元中的数据的二进制函数。

7. 发明授权

US08238173B2 Using storage cells to perform computation 有权
标题翻译：使用存储单元执行计算
公开(公告)号：US08238173B2
公开(公告)日：2012-08-07
申请号：US12503916
申请日：2009-07-16
申请人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
发明人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C29/34 , G11C15/043
摘要： An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.
摘要翻译：存储器内部处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少两个单元的数据的布尔函数输出。另一个实施例示出了没有任何单元内比较器电路的内容可寻址存储器（CAM）单元。

8. 发明授权

US08711638B2 Using storage cells to perform computation 有权
标题翻译：使用存储单元执行计算
公开(公告)号：US08711638B2
公开(公告)日：2014-04-29
申请号：US13437956
申请日：2012-04-03
申请人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
发明人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
IPC分类号： G11C7/10 , G11C29/34
CPC分类号： G11C29/34 , G11C15/043
摘要： A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells.
摘要翻译：一种方法包括激活至少两行纯存储器单元并读取激活的存储器单元的至少一列，该读取产生存储在激活的存储单元中的数据的二进制函数。

9. 发明授权

US08332580B2 System, method and apparatus for memory with embedded associative section for computations 有权
标题翻译：用于计算的嵌入式联想部分的存储器的系统，方法和装置
公开(公告)号：US08332580B2
公开(公告)日：2012-12-11
申请号：US12464937
申请日：2009-05-13
申请人： Avidan Akerib , Eli Ehrman , Josh Meir , Moshe Meyassed , Oren Agam , Yair Alpern
发明人： Avidan Akerib , Eli Ehrman , Josh Meir , Moshe Meyassed , Oren Agam , Yair Alpern
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
摘要翻译：集成电路器件包括半导体衬底和随机存取存储器（RAM）单元阵列，其被布置在第一列中的衬底上，并被配置为存储数据。设备中的计算部分包括相关存储器单元，其被布置在第二列中的衬底上，其与RAM单元的相应的第一列对齐并且与相应的第一列通信，以便从阵列接收数据并且对数据执行关联计算。

10. 发明申请

US20090254694A1 MEMORY DEVICE WITH INTEGRATED PARALLEL PROCESSING 审中-公开
标题翻译：具有集成并行处理的存储器件
公开(公告)号：US20090254694A1
公开(公告)日：2009-10-08
申请号：US12113475
申请日：2008-05-01
申请人： Eli Ehrman , Yoav Lavi , Avidan Akerib
发明人： Eli Ehrman , Yoav Lavi , Avidan Akerib
IPC分类号： G06F12/00
CPC分类号： G11C7/1006
摘要： A method for data processing includes accepting input data words including bits for storage in a memory, which includes multiple memory cells arranged in rows and columns. The accepted data words are stored so that the bits of each data word are stored in more than a single row of the memory. A data processing operation is performed on the stored data words by applying a sequence of one or more bit-wise operations to at least one row of the memory, so as to produce a result that is stored in one or more of the rows of the memory.
摘要翻译：一种用于数据处理的方法包括接收包括用于存储在存储器中的位的输入数据字，其包括以行和列排列的多个存储器单元。存储所接受的数据字，使得每个数据字的位被存储在存储器的多行中。对存储的数据字执行数据处理操作，通过对存储器的至少一行施加一个或多个逐位操作的序列，以产生存储在存储器的一行或多行中的结果记忆。

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