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1. 发明授权

US6067648A Programmable pulse generator 失效
标题翻译：可编程脉冲发生器
公开(公告)号：US6067648A
公开(公告)日：2000-05-23
申请号：US32968
申请日：1998-03-02
申请人： Paul R. Hunter , Archer R. Lawrence , Jack C. Little
发明人： Paul R. Hunter , Archer R. Lawrence , Jack C. Little
IPC分类号： G01R31/319 , G11C29/56 , H03K5/15 , G11C29/00 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1502 , G11C29/56 , G01R31/31921
摘要： A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.
摘要翻译：数字可编程延迟，提供一系列以脉冲延迟和触发延迟编程的脉冲，以控制存储器模块测试系统的操作。

2. 发明授权

US5812472A Nested loop method of identifying synchronous memories 失效
标题翻译：识别同步存储器的嵌套循环方法
公开(公告)号：US5812472A
公开(公告)日：1998-09-22
申请号：US895305
申请日：1997-07-16
申请人： Archer R. Lawrence , Jack C. Little
发明人： Archer R. Lawrence , Jack C. Little
IPC分类号： G06F11/22 , G11C29/14 , G11C7/00
CPC分类号： G06F11/2289 , G11C29/14
摘要： A nested loop method for use in a memory test system to identify the width, depth, control line configuration, and part type of a synchronous memory, wherein bit patterns are retrieved from tables representative of a plurality of synchronous memories during execution of nested loops, from outer loop to inner loop, in the order of bank loop, RE loop, CE loop, CS loop, DQMB loop, and part type loop, and bits of an entry of a table occurring after a given entry are either a member of a superset or do not intersect bits of previous entries, and bits of an entry preceding the given entry are either a member of a subset or do not intersect bits of the given entry.
摘要翻译：一种在存储器测试系统中用于识别同步存储器的宽度，深度，控制线配置和部件类型的嵌套循环方法，其中在执行嵌套循环期间从表示多个同步存储器的表中检索位模式，从外循环到内循环，按照循环，RE循环，CE循环，CS循环，DQMB循环和部分类型循环的顺序，在给定条目之后发生的表的条目的位是超集或不与先前条目的位相交，并且给定条目之前的条目的位是子集的成员或不与给定条目的位相交。

3. 发明授权

US06892328B2 Method and system for distributed testing of electronic devices 有权
标题翻译：电子设备分布式测试方法与系统
公开(公告)号：US06892328B2
公开(公告)日：2005-05-10
申请号：US09966541
申请日：2001-09-27
申请人： Joseph C. Klein , Jack C. Little , Paul R. Hunter , Archer R. Lawrence
发明人： Joseph C. Klein , Jack C. Little , Paul R. Hunter , Archer R. Lawrence
IPC分类号： G11C29/56 , G06F11/00
CPC分类号： G11C29/56
摘要： A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network. A test design host and a global data master also interface with the network to aid the design and storage of test recipes. The distributed test method and system advantageously improves flexibility of testing over a geographically disbursed area and with divergent test recipes and devices under test.
摘要翻译：分布式测试仪方法和系统通过网络向测试站点传送测试电子样本，用于测试电子设备。测试站点将测试配方转换为测试指令，以便由确定电子设备状态的测试引擎执行。例如，在用于测试存储器的测试器中，定义测试配方并与主机一起存储以确定测试数据，以便在测试位置的待测存储器件上进行存储。主机通过网络控制测试配方的执行。测试配方被定义并存储在通过网络传输到测试站点处理器的XML格式的数据文件中。测试站点处理器将XML格式的数据转换成测试指令，以供测试引擎执行。测试引擎确定被测试的存储器件是否准确地存储数据，并通过网络将诸如错误存储的数据的结果提供给主计算机。测试设计主机和全局数据主机也与网络接口，以帮助设计和存储测试配方。分布式测试方法和系统有利地提高了在地理上支付的区域上的测试的灵活性，并且具有不同的测试配方和被测设备。

4. 发明授权

US6064948A Tester systems 失效
标题翻译：测试仪系统
公开(公告)号：US6064948A
公开(公告)日：2000-05-16
申请号：US33364
申请日：1998-03-02
申请人： Michael S. West , Archer R. Lawrence , Paul R. Hunter , Jack C. Little
发明人： Michael S. West , Archer R. Lawrence , Paul R. Hunter , Jack C. Little
IPC分类号： G01R31/3183 , G01R31/319 , G01R31/26
CPC分类号： G01R31/318307 , G01R31/3191
摘要： A tester for use with a device under test includes a processor, a signal timing editor to create representations of signal waveforms and associated times, and a test program executable on the processor that schedules events based on information from the signal timing editor. The test program schedules different delays for the events to compensate for variations in time delays between different signals coupled to the device under test.
摘要翻译：与被测设备一起使用的测试器包括处理器，用于创建信号波形和相关时间表示的信号定时编辑器，以及可在处理器上执行的测试程序，其基于来自信号定时编辑器的信息调度事件。测试程序为事件调度不同的延迟，以补偿耦合到被测器件的不同信号之间的时间延迟的变化。

5. 发明授权

US5999468A Method and system for identifying a memory module configuration 有权
标题翻译：用于识别内存模块配置的方法和系统
公开(公告)号：US5999468A
公开(公告)日：1999-12-07
申请号：US193804
申请日：1998-11-17
申请人： Allen B. Lawrence
发明人： Allen B. Lawrence
IPC分类号： G06F11/22 , G11C5/00 , G11C29/08 , G11C7/00
CPC分类号： G11C29/08 , G06F11/2289
摘要： A method and system for identifying the configuration of a memory module from a list of memory module parts uses contact test results on the memory module to determine data, control and address lines connected to the module. The memory module data, control and address line configurations as determined by the contact test are compared with data, control and address line configuration information from a list of potential memory parts. Non-matching memory parts from the list are eliminated from further testing, resulting in a reduced number of read and write cycles used by the tester to identify parts located on the memory module. The tester counts the number of data lines connected to the memory module to determine the width of the memory parts. The tester then performs a read and write operation to determine the number of memory banks located on the memory module and the control line configuration of the memory module. The tester then runs address tests for matching parts of the parts list to determine the depth of the parts loaded on the module, allowing identification of the parts loaded on the module, and resulting in identification of the memory module's configuration.
摘要翻译：用于从存储器模块部件列表中识别存储器模块的配置的方法和系统使用存储器模块上的接触测试结果来确定连接到模块的数据，控制和地址线。由接触测试确定的存储器模块数据，控制和地址线配置与潜在存储器部件列表中的数据，控制和地址线配置信息进行比较。来自列表的不匹配的存储器部件从进一步测试中消除，导致测试器使用的读取和写入周期数量减少，以识别位于存储器模块上的部件。测试仪将连接到存储器模块的数据线的数量进行计数，以确定存储器部件的宽度。然后，测试仪执行读写操作，以确定存储器模块上的存储器组的数量和存储器模块的控制线配置。测试仪然后运行地址测试，以匹配部件列表中的部件，以确定加载在模块上的部件的深度，从而可以识别加载在模块上的部件，从而识别内存模块的配置。

6. 发明授权

US6008664A Parametric test system and method 失效
标题翻译：参数测试系统及方法
公开(公告)号：US6008664A
公开(公告)日：1999-12-28
申请号：US33285
申请日：1998-03-02
申请人： Allen Jett , Archer R. Lawrence
发明人： Allen Jett , Archer R. Lawrence
IPC分类号： G01R19/00 , G01R31/02 , G01R31/26
CPC分类号： G01R19/0023
摘要： A system and method for reducing voltage stabilization time in a leakage current test system, and thereby reducing the time for measuring leakage currents in the I/O pins of an IC chip including CMOS DRAMs is disclosed. The method and system of the present invention accelerates leakage current testing time by precharging the capacitance of the I/O pins under test to a voltage near the settled voltage level, before measuring leakage current at the I/O pin contact points of packaged IC chips and assembled IC modules, and indicating when an I/O pin is defective.
摘要翻译：公开了一种用于降低泄漏电流测试系统中的电压稳定时间的系统和方法，从而减少了测量包括CMOS DRAM的IC芯片的I / O引脚中的漏电流的时间。本发明的方法和系统在测量封装的IC芯片的I / O引脚接触点处的泄漏电流之前，通过将被测试的I / O引脚的电容预先充电到稳定的电压电平附近来加速泄漏电流测试时间并组装IC模块，并指示I / O引脚何时有故障。

7. 发明授权

US5995424A Synchronous memory test system 失效
标题翻译：同步内存测试系统
公开(公告)号：US5995424A
公开(公告)日：1999-11-30
申请号：US895307
申请日：1997-07-16
申请人： Archer R Lawrence , Jack C Little
发明人： Archer R Lawrence , Jack C Little
IPC分类号： G01R31/319 , G11C29/02 , G11C29/10 , G11C29/44 , G11C29/50 , G11C29/56 , G11C7/00
CPC分类号： G11C29/021 , G01R31/31908 , G01R31/31914 , G01R31/31915 , G11C29/02 , G11C29/10 , G11C29/44 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C11/401 , G11C2029/5002 , G11C2029/5004
摘要： An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing, data in the memory device.
摘要翻译：一种用于识别测试参数的自动化，便携式和时间保守的存储器测试系统，包括包括SDRAM和SGRAM的各种同步存储器中的任何一个的类型，控制线配置，深度，宽度，访问时间和突发特征，以及是否 IC芯片，银行，板或模块，而不需要对被识别的存储器件进行硬件修改或添加，并且不需要在存储器件中存储测试图案或表征数据。

8. 发明授权

US5508700A Capacitance sensitive switch and switch array 失效
标题翻译：电容敏感开关和开关阵列
公开(公告)号：US5508700A
公开(公告)日：1996-04-16
申请号：US214265
申请日：1994-03-17
申请人： Thomas M. Taylor , Mitchell G. Burton
发明人： Thomas M. Taylor , Mitchell G. Burton
IPC分类号： G01V3/08 , G01R27/26 , H03K17/955 , H03K17/96
CPC分类号： H03K17/955 , H03K17/962 , H03K2217/960715
摘要： A capacitance-sensitive switch unit including a capacitive element operable to produce an effective capacitance dependent upon the physical proximity of objects relative thereto, a first selector signal input connected to the capacitive element to enable a first input signal to charge the effective capacitance, a threshold signal producing circuit connected to the capacitive element, for producing a threshold signal which is rendered active when the effective capacitance charges to a pre-defined potential, a switching circuit for selectively connecting the capacitive element to the threshold signal producing circuit in response to a switching signal and a discharge control circuit connected to the capacitive element, for selectively discharging the effective capacitance independently of the input signal, in response to a discharge signal. Also disclosed is a switch array employing structure similar to the above.
摘要翻译：一种电容敏感开关单元，包括电容元件，其可操作以根据物体相对于物体的物理接近度产生有效电容;连接到电容元件的第一选择器信号输入，以使第一输入信号对有效电容充电;阈值连接到电容元件的信号产生电路，用于产生当有效电容充电到预定电位时被激活的阈值信号;用于响应于开关选择性地将电容元件连接到阈值信号产生电路的开关电路信号和放电控制电路，连接到电容元件，用于响应于放电信号而选择性地放电与输入信号无关的有效电容。还公开了采用与上述类似的结构的开关阵列。

9. 发明授权

US09626264B2 Memory device test apparatus and method having multiple memory devices connected to downstream ports of a PCI express switch at the same time 有权
公开(公告)号：US09626264B2
公开(公告)日：2017-04-18
申请号：US14661390
申请日：2015-03-18
申请人： Neosem Inc. , Tanisys Technology, Inc.
发明人： Dong Hyun Yeom , Bruce A. Parker
IPC分类号： G06F13/42 , G06F11/26 , G06F13/40 , G01R31/3193
CPC分类号： G06F11/26 , G01R31/3193 , G06F13/4022 , G06F13/4282 , G11C16/00 , G11C29/00 , G11C29/38
摘要： Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test.

10. 发明申请

US20020042897A1 Method and system for distributed testing of electronic devices 有权
标题翻译：电子设备分布式测试方法与系统
公开(公告)号：US20020042897A1
公开(公告)日：2002-04-11
申请号：US09966541
申请日：2001-09-27
申请人： Tanisys Technology Inc.
发明人： Joseph C. Klein , Jack C. Little , Paul R. Hunter , Archer R. Lawrence
IPC分类号： G11C029/00
CPC分类号： G11C29/56
摘要： A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network. A test design host and a global data master also interface with the network to aid the design and storage of test recipes. The distributed test method and system advantageously improves flexibility of testing over a geographically disbursed area and with divergent test recipes and devices under test.
摘要翻译：分布式测试仪方法和系统通过网络向测试站点传送测试电子样本，用于测试电子设备。测试站点将测试配方转换为测试指令，以便由确定电子设备状态的测试引擎执行。例如，在用于测试存储器的测试器中，定义测试配方并与主机一起存储以确定测试数据，以便在测试位置的待测存储器件上进行存储。主机通过网络控制测试配方的执行。测试配方被定义并存储在通过网络传输到测试站点处理器的XML格式的数据文件中。测试站点处理器将XML格式的数据转换成测试指令，以供测试引擎执行。测试引擎确定被测试的存储器件是否准确地存储数据，并通过网络将诸如错误存储的数据的结果提供给主计算机。测试设计主机和全局数据主机也与网络接口，以帮助设计和存储测试配方。分布式测试方法和系统有利地提高了在地理上支付的区域上的测试的灵活性，并且具有不同的测试配方和被测设备。

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