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1. 发明申请

US20120228613A1 METHOD OF MANUFACTURING SEMICONDUCTOR WAFER, AND COMPOSITE BASE AND COMPOSITE SUBSTRATE FOR USE IN THAT METHOD 有权
标题翻译：制造半导体波形的方法以及用于该方法的复合基底和复合基板
公开(公告)号：US20120228613A1
公开(公告)日：2012-09-13
申请号：US13107286
申请日：2011-05-13
申请人： Yuki SEKI , Issei Satoh , Koji Uematsu , Yoshiyuki Yamamoto
发明人： Yuki SEKI , Issei Satoh , Koji Uematsu , Yoshiyuki Yamamoto
IPC分类号： H01L29/04 , B32B3/00 , H01L27/12 , H01L29/02 , H01L21/762 , H01L29/22
CPC分类号： H01L29/0684 , B32B2264/102 , B32B2307/704 , B32B2457/14 , H01L21/76254
摘要： A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base. Thus, a method of manufacturing a semiconductor wafer capable of efficiently manufacturing the semiconductor wafer regardless of the type of a base, and a composite base and a composite substrate suitably used in that manufacturing method are provided to efficiently manufacture a semiconductor device.
摘要翻译：本发明的制造半导体晶片的方法包括以下步骤：通过在基底上形成表面RMS粗糙度不大于1.0nm的基面平坦化层来获得复合基底; 通过将半导体晶体层附着到所述复合基底的所述基面平坦化层所在的一侧来获得复合基板; 在复合衬底的半导体晶体层上生长至少一个半导体层; 以及通过湿法蚀刻去除基底表面平坦化层，从而将半导体晶体层与基底分离，从而获得包括半导体晶体层和半导体层的半导体晶片。因此，提供一种制造半导体晶片的方法，而不管基底的类型如何，以及适用于该制造方法的复合基底和复合基底都能有效地制造半导体晶片，以有效地制造半导体器件。

2. 发明申请

US20040165871A1 WAFER HOLDER FOR SEMICONDUCTOR MANUFACTURING DEVICE AND SEMICONDUCTOR MANUFACTURING DEVICE IN WHICH THE HOLDER IS INSTALLED 审中-公开
标题翻译：用于半导体制造装置的保持器和安装支架的半导体制造装置
公开(公告)号：US20040165871A1
公开(公告)日：2004-08-26
申请号：US10708224
申请日：2004-02-18
申请人： SUMITOMO ELECTRIC INDUSTIRES, LTD.
发明人： Masuhiro Natsuhara , Hirohiko Nakata , Manabu Hashikura
IPC分类号： F27D011/00 , F27B005/14
CPC分类号： H01L21/67103 , F27D5/0037 , H01L21/68714
摘要： Affords for semiconductor manufacturing devices a wafer holder and a semiconductor manufacturing device in which it is installed, where in the wafer holder, which has a wafer-carrying side, the isothermal quality of its wafer-carrying side is enhanced. A shaft that supports the wafer holder having a wafer-carrying side is joined to the wafer holder, wherein by making a distance a between the center axis of the shaft and the axial center of the wafer-carrying side 5% or less of the diameter L of the wafer-carrying side, the temperature distribution in the surface of a wafer set into place on the holder can be brought to within null1.0%. Moreover, making the distance a 1% or less of the diameter L enables the temperature distribution to be brought to within null0.5%.
摘要翻译：为半导体制造装置提供晶片保持器和其中安装有半导体制造装置，其中具有晶片承载侧的晶片保持器中，其晶片承载侧的等温质量得到增强。支撑具有晶片承载侧的晶片保持器的轴接合到晶片保持器，其中通过使轴的中心轴与晶片承载侧的轴向中心之间的距离a为直径的5％以下在晶片承载侧的L个中，在保持器上的位置上的晶片的表面的温度分布可以达到±1.0％以内。此外，使距离为直径L的1％以下能够使温度分布在±0.5％以内。

3. 发明授权

US12007919B2 In-vehicle communication device and vehicle communication method 有权
公开(公告)号：US12007919B2
公开(公告)日：2024-06-11
申请号：US17755513
申请日：2020-08-13
申请人： AutoNetworks Technologies, Ltd. , Sumitomo Wiring Systems, Ltd. , Sumitomo Electric Industries, Ltd.
发明人： Yuanjun Xian , Takeshi Hagihara , Makoto Mashita , Nobuyuki Kobayashi , Takehiro Kawauchi , Tatsuya Izumi , Akihito Iwata , Yusuke Yamamoto
IPC分类号： G06F13/26 , G06F13/24 , H04W4/48 , H04L49/351
CPC分类号： G06F13/24 , H04W4/48 , H04L49/351
摘要： An in-vehicle communication device for transmitting and receiving a signal by a predetermined communication protocol related to Ethernet® (registered trademark), the in-vehicle communication device comprising: a control circuit configured to generate transmission data including interrupt data inserted into an inter-frame gap between Ethernet frames; and a PHY unit having a communication circuit configured to convert the transmission data generated by the control circuit into a signal and transmit the signal.

4. 发明申请

US20140346530A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140346530A1
公开(公告)日：2014-11-27
申请号：US14285181
申请日：2014-05-22
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Ken NAKATA , Keiichi YUI , Hiroyuki ICHIKAWA , Isao MAKABE , Tsuyoshi KOUCHI
IPC分类号： H01L29/778 , H01L21/02 , H01L29/66
CPC分类号： H01L21/0262 , H01L21/02378 , H01L21/02458 , H01L21/02494 , H01L21/0254 , H01L29/2003 , H01L29/7786
摘要： A semiconductor device according to an embodiment of the present invention includes a SiC substrate, an AlN layer provided on the SiC substrate and having a maximum valley depth Rv of 5 nm or less in an upper surface, a channel layer provided on the AlN layer and composed of a nitride semiconductor, an electron supply layer provided on the channel layer and having a greater band gap than the channel layer, and a gate electrode, a source electrode and a drain electrode provided on the electron supply layer.
摘要翻译：根据本发明实施例的半导体器件包括SiC衬底，设置在SiC衬底上的AlN层，并且在上表面具有5nm或更小的最大谷深度Rv，设置在AlN层上的沟道层和由氮化物半导体构成，电子供给层设置在沟道层上并且具有比沟道层更大的带隙，以及设置在电子供给层上的栅电极，源电极和漏电极。

5. 发明申请

US20110163323A1 GaN SINGLE CRYSTAL SUBSTRATE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译： GaN单晶基板及其制造方法
公开(公告)号：US20110163323A1
公开(公告)日：2011-07-07
申请号：US13045886
申请日：2011-03-11
申请人： Kensaku Motoki , Takuji Okahisa , Naoki Matsumoto
发明人： Kensaku Motoki , Takuji Okahisa , Naoki Matsumoto
IPC分类号： H01L29/20
CPC分类号： C30B25/00 , C30B25/02 , C30B29/406 , H01L21/02395 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L33/007
摘要： The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.
摘要翻译：制造GaN单晶衬底的方法包括掩模层形成步骤，在GaAs衬底2上形成具有彼此分离设置的多个开口窗口10的掩模层8; 以及在掩模层8上生长由GaN制成的外延层12的外延层生长步骤。

6. 发明申请

US20140073101A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20140073101A1
公开(公告)日：2014-03-13
申请号：US13958151
申请日：2013-08-02
申请人： Sumitomo Electric Industries, Ltd.
发明人： Yu Saitoh , Takeyoshi Masuda , Hideki Hayashi
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/02236 , H01L21/02255 , H01L21/049 , H01L21/3065 , H01L29/045 , H01L29/1608 , H01L29/401 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/7827 , Y10S438/931
摘要： A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall.
摘要翻译：具有侧壁和底部的沟槽形成在碳化硅衬底中。形成沟槽绝缘膜以覆盖底部和侧壁。形成硅膜以填充沟槽，沟槽绝缘膜插入其间。对硅膜进行蚀刻，以便在沟槽绝缘膜之间插入设置在底部的硅膜的一部分。从侧壁去除沟槽绝缘膜。通过氧化硅膜，形成底部绝缘膜。在侧壁上形成侧壁绝缘膜。

7. 发明申请

US20110292955A1 TUNABLE SEMICONDUCTOR LASER DIODE 有权
标题翻译： TUNNABLE SEMICONDUCTOR激光二极管
公开(公告)号：US20110292955A1
公开(公告)日：2011-12-01
申请号：US13115301
申请日：2011-05-25
申请人： Toshimitsu KANEKO
发明人： Toshimitsu KANEKO
IPC分类号： H01S5/06
CPC分类号： H01S5/06258 , B82Y20/00 , H01S5/0265 , H01S5/028 , H01S5/0425 , H01S5/0612 , H01S5/06256 , H01S5/1209 , H01S5/1212 , H01S5/1215 , H01S5/34306
摘要： A tunable LD with reduced number of the butt joint is disclosed. The tunable LD includes the reflector and a waveguide core. The reflector includes a plurality of segments each having a grating region and a space region adjacent to the grating region. The waveguide core includes a gain region extending in two segments adjacent to each other and a tuning region extending in two segments adjacent to each other and also adjacent to the segment for the gain region.
摘要翻译：公开了一种具有对接接头数量减少的可调LD。可调谐LD包括反射器和波导芯。反射器包括多个段，每个段具有光栅区域和与光栅区域相邻的空间区域。波导芯包括在彼此相邻的两个部分中延伸的增益区域和在彼此相邻并且邻近于用于增益区域的段的两个段中延伸的调谐区域。

8. 发明申请

US20110108853A1 COMPOUND SEMICONDUCTOR DEVICE 失效
标题翻译：化合物半导体器件
公开(公告)号：US20110108853A1
公开(公告)日：2011-05-12
申请号：US12835003
申请日：2010-07-13
申请人： Masahiro ADACHI , Shinji Tokuyama , Koji Katayama
发明人： Masahiro ADACHI , Shinji Tokuyama , Koji Katayama
IPC分类号： H01L29/24 , H01L29/20
CPC分类号： H01L33/40 , H01L33/32 , H01L33/34
摘要： A compound semiconductor device having reduced contact resistance to an electrode is provided. The compound semiconductor device includes an n-substrate 3 comprising a hexagonal compound semiconductor GaN and having surfaces S1 and S2; an n-electrode 13 formed on the surface S1 of the n-substrate 3; a layered product having an n-cladding layer 5, an active layer 7, a p-cladding layer 9, and a contact layer 11 formed on the surface S2 of the n-substrate 3; and a p-electrode 15 formed on the p-cladding layer 9. The number of N atoms contained on the surface S1 of the n-substrate 3 is more than the number of Ga atoms contained on the surface S1. The electrode formed on the surface S1 is an n-electrode 13. The surface S1 has an oxygen concentration of not more than 5 atomic percent. The number of Ga atoms contained on the surface S3 of the contact layer 11 is more than the number of N atoms contained on the surface S3. The electrode formed on the surface S3 is a p-electrode 15. The surface S3 has an oxygen concentration of not more than 5 atomic percent.
摘要翻译：提供具有降低的与电极的接触电阻的化合物半导体器件。该化合物半导体器件包括包含六方晶系化合物半导体GaN并具有表面S1和S2的n衬底3; 形成在n基板3的表面S1上的n电极13; 具有形成在n基板3的表面S2上的n包层5，有源层7，p包覆层9和接触层11的层叠体，以及形成在p包覆层9上的p电极15.包含在n基板3的表面S1上的N原子的数量大于表面S1上包含的Ga原子的数量。形成在表面S1上的电极是n电极13.表面S1的氧浓度不大于5原子％。接触层11的表面S3上所含的Ga原子数多于表面S3所含的N原子数。形成在表面S3上的电极是p电极15.表面S3的氧浓度不大于5原子％。

9. 发明申请

US20070128359A1 PRODUCTION APPARATUS FOR PRODUCING GALLIUM NITRIDE FILM SEMICONDUCTOR AND CLEANING APPARATUS FOR EXHAUST GAS 审中-公开
标题翻译：用于生产氮化钛薄膜半导体的生产设备和用于排气的清洁装置
公开(公告)号：US20070128359A1
公开(公告)日：2007-06-07
申请号：US11674341
申请日：2007-02-13
申请人： Kenji OTSUKA , Naoki Muranaga , Kikurou Takemoto
发明人： Kenji OTSUKA , Naoki Muranaga , Kikurou Takemoto
IPC分类号： C23C16/00
CPC分类号： C30B25/02 , B01D53/58 , B01D53/77 , B01D2258/0216 , C23C14/0617 , C23C16/301 , C23C16/4401 , C23C16/4412 , C23C16/4488 , C30B29/406
摘要： There are disclosed a production apparatus for producing a gallium nitride film semiconductor by HVPE process, a cleaning apparatus for cleaning exhaust gas coming from the above apparatus and an overall production plant for producing a gallium nitride film semiconductor by HVPE process. Therein exhaust piping for exhaust gas in the production apparatus, introduction piping for the cleaning apparatus and exhaust gas piping which connects the production apparatus and the cleaning apparatus are each composed of an electroconductive corrosion-resistant material and are each electrically grounded, thereby surely preventing electrostatic charging due to friction between ammonium chloride powders in the exhaust gas and inside walls of exhaust gas piping, and markedly enhancing operational safety.
摘要翻译：公开了一种通过HVPE工艺制造氮化镓膜半导体的制造装置，用于清洁从上述装置排出的废气的清洁装置和通过HVPE处理制造氮化镓膜半导体的整体生产装置。在制造装置中的废气排气管道中，连接制造装置和清洗装置的清洗装置和排气管路的导入配管各自由导电性耐腐蚀材料构成，各自电接地，从而可靠地防止静电由于废气中的氯化铵粉末与废气管道的内壁之间的摩擦而引起的充电，并且显着提高了操作安全性。

10. 发明申请

US20040000692A1 METHOD AND DEVICE FOR DETERMINING BACKGATE CHARACTERISTICS 失效
标题翻译：用于确定背板特性的方法和装置
公开(公告)号：US20040000692A1
公开(公告)日：2004-01-01
申请号：US10249710
申请日：2003-05-01
申请人： SUMITOMO ELECTRIC INDUSTIRES, LTD.
发明人： Masashi Yamashita , Mitsutaka Tsubokura , Makoto Kiyama
IPC分类号： H01L029/76
CPC分类号： H01L22/14
摘要： Backgate-characteristics determination method and device that make for curtailing the fabrication of semiconductor circuit elements having defective backgate-characteristics. Initially a first C-V curve 30 representing the relation between a voltage applied to the obverse face of a wafer 20 serving as a substrate for semiconductor circuit elements, and its capacitance, is found. Next, a second C-V curve 32 is found through applying a voltage to the reverse face of the wafer 20. The backgate characteristics for the semiconductor circuit elements are determined based on a voltage-shift amount 34 for the wafer 20, found from the first C-V curve 30 and the second C-V curve 32.
摘要翻译：背栅特性确定方法和装置，其用于抑制具有缺陷背栅特性的半导体电路元件的制造。首先，找到表示施加到用作半导体电路元件的基板的晶片20的正面的电压与其电容之间的关系的第一C-V曲线30。接下来，通过向晶片20的反面施加电压来发现第二CV曲线32.半导体电路元件的背栅特性基于从第一CV找到的晶片20的电压移位量34来确定曲线30和第二CV曲线32。

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