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1. 发明授权

US4651305A Sense amplifier bit line isolation scheme 失效
标题翻译：感应放大器位线隔离方案
公开(公告)号：US4651305A
公开(公告)日：1987-03-17
申请号：US700571
申请日：1985-02-11
申请人： Harold L. Davis
发明人： Harold L. Davis
IPC分类号： G11C7/00 , G11C17/12
CPC分类号： G11C17/126
摘要： In a CMOS ROM memory arrangement, the use of the least significant column address bit to perform the dual function of even/odd bit line select and the disconnection of the selected bit line (17' and 17") from the sense amplifier (66) driven, in order to reduce its capacitive load, prior to the time of latching the information into the sense amplifier (66).
摘要翻译：在CMOS ROM存储器装置中，使用最低有效列地址位来执行偶/奇位线选择的双重功能以及所选位线（17'和17“）与读出放大器（66）的断开）驱动，以便在将信息锁存到读出放大器（66）之前，减小其电容性负载。

2. 发明授权

US4627787A Chip selection in automatic assembly of integrated circuit 失效
标题翻译：集成电路自动组装中的芯片选择
公开(公告)号：US4627787A
公开(公告)日：1986-12-09
申请号：US592156
申请日：1984-03-22
申请人： Robert H. Bond , Steven Swendrowski , Michael A. Olla , Barry L. Morrison , Ricky Parkinson , Linn Garrison , John D. Pace
发明人： Robert H. Bond , Steven Swendrowski , Michael A. Olla , Barry L. Morrison , Ricky Parkinson , Linn Garrison , John D. Pace
IPC分类号： H01L21/50 , B25J7/00 , H01L21/301 , H01L21/52 , H01L21/67 , H01L21/683 , B25J9/00
CPC分类号： H01L21/6835 , Y10S156/93 , Y10T156/11 , Y10T156/19 , Y10T29/49117
摘要： A method for removing selected integrated circuit dice from a wafer array of dice sequentially moves a striker above a tape to the underside of which the array is mounted and the knocks a die down from the array of dice into a receptacle for transport to further processing stages.
摘要翻译：用于从晶片阵列的骰子移除所选择的集成电路晶片的方法依次将位于磁带上方的撞针移动到安装阵列的下侧，并将模具从模具阵列中下降到一个插座中，以便传输到另外的处理阶段。

3. 发明授权

US4626713A Trip-point clamping circuit for a semiconductor device 失效
标题翻译：用于半导体器件的触点钳位电路
公开(公告)号：US4626713A
公开(公告)日：1986-12-02
申请号：US648093
申请日：1984-09-06
申请人： Robert D. Lee
发明人： Robert D. Lee
IPC分类号： H03K5/007 , H03K17/14
CPC分类号： H03K5/007 , H03K17/145
摘要： A trip point clamping circuit for maintaining the voltage level at a node of connection to a sense arrangement including an inverter within defined bounds at the trip point of the inverter, the clamping circuit including a reference voltage, a source of similar current levels, a switch for turning the clamping circuit on and off, and a transistor responsive to the voltage level at said node of connection.
摘要翻译：一种跳闸点钳位电路，用于将连接到包括反相器的感测装置的节点处的电压电平保持在所述逆变器的跳变点处的限定范围内，所述钳位电路包括参考电压，类似电流电平的源，开关用于打开和关闭钳位电路，以及响应于所述连接节点处的电压电平的晶体管。

4. 发明授权

US4626167A Manipulation and handling of integrated circuit dice 失效
标题翻译：集成电路骰子的操作和处理
公开(公告)号：US4626167A
公开(公告)日：1986-12-02
申请号：US592151
申请日：1984-03-22
申请人： Robert H. Bond , Steven Swendrowski , Michael A. Olla , Barry L. Morrison
发明人： Robert H. Bond , Steven Swendrowski , Michael A. Olla , Barry L. Morrison
IPC分类号： H01L21/67 , H01L21/00 , H01L21/301 , H01L21/52 , H01L21/68 , H01L21/683 , B32B31/04
CPC分类号： H01L21/67144 , H01L21/6838
摘要： A method for inverting and handling integrated circuit dice employs rotating apparatus for rotating a chip carrier by 180 degrees to invert and transfer dice from one set of receptacles to another; together with an apparatus for precisely aligning dice resting at random positions within a set of oversized receptacles.
摘要翻译：一种用于反转和处理集成电路骰子的方法采用旋转装置，用于将芯片载体旋转180度，以将骰子从一组插座转移到另一组; 以及用于精确对准在一组超大容器内的随机位置休息的骰子的装置。

5. 发明授权

US4609985A Microcomputer with severable ROM 失效
标题翻译：具有可分割ROM的微型计算机
公开(公告)号：US4609985A
公开(公告)日：1986-09-02
申请号：US454799
申请日：1982-12-30
申请人： Harold W. Dozier
发明人： Harold W. Dozier
IPC分类号： G06F9/26 , G06F13/00
CPC分类号： G06F9/268
摘要： A microcomputer has provision for both on-chip ROM (on the same chip as the CPU) and off-chip ROM and which may operate with only on-chip ROM as only off-chip ROM has the hardware capability to disable on-chip ROM permanently, so that chips having defective ROM may be salvaged by being converted to computer chips that use only off-chip ROM.
摘要翻译：微型计算机既提供片上ROM（与CPU相同的芯片）和片外ROM，并且只能使用片上ROM，因为只有片外ROM具有禁止片内ROM的硬件能力永久地使得具有缺陷ROM的芯片可以通过转换成仅使用片外ROM的计算机芯片来进行抢救。

6. 发明授权

US4549336A Method of making MOS read only memory by specified double implantation 失效
标题翻译：通过指定的双重注入制作MOS只读存储器的方法
公开(公告)号：US4549336A
公开(公告)日：1985-10-29
申请号：US608539
申请日：1984-05-09
申请人： Sheppard Douglas P.
发明人： Sheppard Douglas P.
IPC分类号： H01L27/088 , H01L27/112 , H01L29/10 , H01L29/78 , H01L21/263
CPC分类号： H01L27/088 , H01L27/112 , H01L29/1041 , H01L29/78
摘要： The power consumption and corresponding speed of an integrated circuit is scaled by means of adjusting the channel width for MOS transistors. A transistor (12) is initially fabricated with a channel (24) having a width W.sub.1. The channel (24) receives a depletion type implant (30) to make the transistor (12) lightly depleted. An enhancement implant (32) is applied to the channel (24) to cover a selected area (24a). The enhancement implant (32) is made substantially stronger than the depletion implant (30). This results in a first section (24a) of the channel (24) having a large threshold voltage while the second section (24b) of channel (24) has a relatively small pinch-off voltage. The size of the second section (24b) is selectively controlled to scale the source-drain current of transistor (12) and the corresponding power consumption of the transistor (12). The method of applying the first and second implants (30, 32) can be easily incorporated into conventional ROM fabrication without the need for additional manufacturing steps.
摘要翻译：通过调整MOS晶体管的沟道宽度来缩放集成电路的功耗和相应的速度。晶体管（12）最初制造有具有宽度W1的通道（24）。通道（24）接收耗尽型注入（30）以使晶体管（12）轻度耗尽。增强植入物（32）被施加到通道（24）以覆盖选定区域（24a）。增强植入物（32）被制成比耗尽植入物（30）更强。这导致通道（24）的第一部分（24a）具有大的阈值电压，而通道（24）的第二部分（24b）具有较小的夹断电压。选择性地控制第二部分（24b）的尺寸以缩放晶体管（12）的源极 - 漏极电流和晶体管（12）的相应功率消耗。施加第一和第二植入物（30,32）的方法可以容易地并入常规的ROM制造中，而不需要额外的制造步骤。

7. 发明授权

US4523110A MOSFET sense amplifier circuit 失效
标题翻译： MOSFET读出放大器电路
公开(公告)号：US4523110A
公开(公告)日：1985-06-11
申请号：US537916
申请日：1983-09-30
申请人： Mark G. Johnson
发明人： Mark G. Johnson
IPC分类号： G11C7/06 , H03K5/24
CPC分类号： G11C7/062
摘要： A MOSFET sense amplifier applies both input signals to both input transistors of a common-gate sense amplifier; each input signal being applied to the source of one input transistor and the gate of the other, thereby effectively doubling the applied input signal.
摘要翻译： MOSFET读出放大器将两个输入信号施加到公共栅极读出放大器的两个输入晶体管; 每个输入信号被施加到一个输入晶体管的源极和另一个的栅极，从而有效地使施加的输入信号加倍。

8. 发明授权

US4508815A Recessed metallization 失效
标题翻译：嵌入金属化
公开(公告)号：US4508815A
公开(公告)日：1985-04-02
申请号：US548465
申请日：1983-11-03
申请人： Paul W. Ackmann , Frank R. Bryant
发明人： Paul W. Ackmann , Frank R. Bryant
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/312 , H01L21/283
CPC分类号： H01L21/32137 , H01L21/32136 , H01L21/7688
摘要： An improved method of planarizing a level of metallization employs a trench in a smooth-surfaced dielectric and a sequence of etching steps to cut the trench locally down to the substrate, while forming the main metallization pattern at the same time.
摘要翻译：平坦化金属化水平的改进方法使用光滑表面电介质中的沟槽和一系列蚀刻步骤，以同时将沟槽局部切割到衬底，同时同时形成主金属化图案。

9. 发明授权

US4492927A Offset voltage compensation circuit 失效
标题翻译：偏移电压补偿电路
公开(公告)号：US4492927A
公开(公告)日：1985-01-08
申请号：US430446
申请日：1982-09-30
申请人： Douglas R. Holberg
发明人： Douglas R. Holberg
IPC分类号： H04M1/50
CPC分类号： H04M1/505
摘要： A dual-tone multi-frequency (DTMF) tone generator circuit (10) produces selected frequency row and column tones which are combined to generate a DTMF signal. Key board scan circuits (42, 44) scan a conventional push-button telephone key board to produce row and column input signals. Row and column fundamental rate signals are generated by fundamental counters (48,76) from a reference signal derived from an external crystal (12). Row and column integration rate signals are generated by integrator counters (50,78) also derived from the reference signal. Specialized row and column clock control signals (SLOPE RATE, SLOPE SIGN, AUTO ZERO) are produced by clock generators (58,82). Row and column integrators (64,92) integrate reference signals to produce discrete voltage steps at the rate of the row and column integration rate signals to produce row and column signals made up of a plurality of segments for each cycle of the signal. Each signal segment comprises a plurality of similar voltage steps having amplitude and polarity determined by the specialized row and column clock signals (SLOPE RATE, SLOPE SIGN). The row and column signals are combined in a summer (68) to produce the DTMF signal.
摘要翻译：双音多频（DTMF）音产生器电路（10）产生被组合以产生DTMF信号的所选频率行和列音调。键板扫描电路（42,44）扫描传统的按钮电话键盘以产生行和列输入信号。行和列基本速率信号由来自外部晶体（12）的参考信号的基本计数器（48,76）产生。行和列积分率信号由也从参考信号导出的积分器计数器（50,78）产生。专门的行和列时钟控制信号（SLOPE RATE，SLOPE SIGN，AUTO ZERO）由时钟发生器（58,82）生成。行和列积分器（64,92）集成参考信号以以行和列积分率信号的速率产生离散电压步长，以产生由信号的每个周期的多个段组成的行和列信号。每个信号段包括具有由专门的行和列时钟信号（SLOPE RATE，SLOPE SIGN）确定的振幅和极性的多个相似的电压阶跃。行和列信号在夏季（68）中组合以产生DTMF信号。

10. 发明授权

US4445266A MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance 失效
标题翻译： MOSFET减少重叠电容并降低互连阻抗的制造工艺
公开(公告)号：US4445266A
公开(公告)日：1984-05-01
申请号：US290833
申请日：1981-08-07
申请人： Chao C. Mai , William M. Whitney , William M. Gosney , Donald J. Gulyas
发明人： Chao C. Mai , William M. Whitney , William M. Gosney , Donald J. Gulyas
IPC分类号： H01L21/8234 , H01L21/22 , H01L21/28
CPC分类号： H01L21/823475 , Y10S438/907
摘要： A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors on P-type semiconductor substrate (10). A layer of oxide (14) is formed on the substrate (10) and then a polysilicon layer (16) is formed on top of the oxide layer (14). A layer of silicon nitride (18) is deposited on top of the polysilicon layer (16). The silicon nitride layer (18), polysilicon layer (16) and oxide layer (14) are selectively etched to form a conductor pattern. The conductor pattern defines a gate electrode and a plurality of interconnecting lines (42) that interconnect transistors to each other and to the peripheral circuits that drive the transistors. The source and drain regions (26 and 28) are ion implanted with arsenic ions. The exposed sidewalls of the polysilicon layer (16) are oxidized lateral and subjacent to the silicon nitride layer (18). The oxidation forms a lateral band of oxide (32) on the polysilicon layer (16) and effectively reduces the conductive width of the polysilicon layer (16). The reduced conductive width reduces the overlap capacitance. The silicon nitride layer (18) is then removed and a layer of tungsten (34) is deposited by hot-wall, low-pressure chemical vapor deposition (LPCVD). The tungsten layer (34) selectively adheres to the polysilicon layer (18) providing a low resistance path for the conductors. The tungsten layer (18) forms both a gate electrode and the low resistance interconnect lines (42) or "runs." A heat treatment may then be applied to the combined tungsten layer (34) and the polysilicon layer (16) to form a composite conductor of tungsten silicide. Thereafter the interconnect lines (42) and gate electrodes are covered by a low temperature oxide (36).
摘要翻译：一种在P型半导体衬底（10）上形成多个互连的金属氧化物半导体场效应晶体管的方法。在衬底（10）上形成氧化层（14），然后在氧化物层（14）的顶部形成多晶硅层（16）。在多晶硅层（16）的顶部上淀积一层氮化硅（18）。选择性地蚀刻氮化硅层（18），多晶硅层（16）和氧化物层（14）以形成导体图案。导体图案限定了栅极电极和多个互连线（42），其互连晶体管和驱动晶体管的外围电路。源极和漏极区域（26和28）离子注入砷离子。多晶硅层（16）的暴露的侧壁在氮化硅层（18）的外侧被氧化。氧化在多晶硅层（16）上形成氧化物（32）的横向带，并且有效地减小了多晶硅层（16）的导电宽度。降低的导电宽度减小了重叠电容。然后去除氮化硅层（18），并通过热壁，低压化学气相沉积（LPCVD）沉积一层钨（34）。钨层（34）选择性地粘附到多晶硅层（18），为导体提供低电阻路径。钨层（18）形成栅极电极和低电阻互连线路（42）或“运行”两者。然后可以对组合的钨层（34）和多晶硅层（16）施加热处理以形成硅化钨的复合导体。此后，互连线（42）和栅电极被低温氧化物（36）覆盖。

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