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1. 发明授权

US4508815A Recessed metallization 失效
标题翻译：嵌入金属化
公开(公告)号：US4508815A
公开(公告)日：1985-04-02
申请号：US548465
申请日：1983-11-03
申请人： Paul W. Ackmann , Frank R. Bryant
发明人： Paul W. Ackmann , Frank R. Bryant
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/312 , H01L21/283
CPC分类号： H01L21/32137 , H01L21/32136 , H01L21/7688
摘要： An improved method of planarizing a level of metallization employs a trench in a smooth-surfaced dielectric and a sequence of etching steps to cut the trench locally down to the substrate, while forming the main metallization pattern at the same time.
摘要翻译：平坦化金属化水平的改进方法使用光滑表面电介质中的沟槽和一系列蚀刻步骤，以同时将沟槽局部切割到衬底，同时同时形成主金属化图案。

2. 发明授权

US06180989B2 Selectively doped electrostatic discharge layer for an integrated circuit sensor 有权
标题翻译：用于集成电路传感器的选择性掺杂静电放电层
公开(公告)号：US06180989B2
公开(公告)日：2001-01-30
申请号：US09144182
申请日：1998-08-31
申请人： Frank R. Bryant , Danielle A. Thomas
发明人： Frank R. Bryant , Danielle A. Thomas
IPC分类号： H01L2982
CPC分类号： G06K9/00053 , Y10S438/931 , Y10S438/953 , Y10S438/958
摘要： A structure and method for creating an integrated circuit passivation structure comprising, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.
摘要翻译：一种用于产生集成电路钝化结构的结构和方法，包括：电路，电介质和金属板，其上设置有电隔离电路的绝缘层，以及沉积以形成钝化结构的放电层，公开了由例如手指引起的静电放电的电路。放电层还包含选择性沉积的掺杂剂以增加静电放电承载能力，同时保持总感测分辨率。

3. 发明授权

US6091132A Passivation for integrated circuit sensors 失效
标题翻译：集成电路传感器的钝化
公开(公告)号：US6091132A
公开(公告)日：2000-07-18
申请号：US995211
申请日：1997-12-19
申请人： Frank R. Bryant
发明人： Frank R. Bryant
IPC分类号： G06K9/00 , H01L23/58
CPC分类号： G06K9/0002
摘要： A structure and method for creating an integrated circuit passivation comprising, a circuit (16) over which an insulating layer (26 and/or 28) is disposed that electrically and hermetically isolates the circuit (16) and a silicon carbide layer (30) to form a passivation (24) to protect a circuit (16), is disclosed.
摘要翻译：一种用于产生集成电路钝化的结构和方法，包括：电路（16），其上设置有绝缘层（26和/或28），电绝缘隔离电路（16）和碳化硅层（30）至形成用于保护电路（16）的钝化（24）。

4. 发明授权

US5894160A Method of forming a landing pad structure in an integrated circuit 失效
公开(公告)号：US5894160A
公开(公告)日：1999-04-13
申请号：US725621
申请日：1996-10-03
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

5. 发明授权

US5736433A Double mask hermetic passivation method providing enhanced resistance to moisture 失效
标题翻译：双面罩密封钝化方法提供增强的耐湿性
公开(公告)号：US5736433A
公开(公告)日：1998-04-07
申请号：US778021
申请日：1996-12-31
申请人： Frank R. Bryant , Abha R. Singh , James A. Cunningham
发明人： Frank R. Bryant , Abha R. Singh , James A. Cunningham
IPC分类号： H01L21/316 , H01L21/66 , H01L21/70 , H01L21/82 , H01L23/31 , H01L23/50
CPC分类号： H01L23/3171 , H01L22/22 , H01L22/14 , H01L2924/0002
摘要： A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging. The second passivation layer overlaps edge portions of the first passivation layer at the bond pads to enhance moisture resistance.
摘要翻译：使用两个钝化层和使用两个掩蔽步骤的保护性外涂层形成钝化结构。第一钝化层形成在晶片之上，并且提供开口以暴露焊盘的部分以测试设备和可熔链路。在测试和激光修复之后，在晶片上形成第二钝化层，然后沉积保护外涂层。保护性外涂层被图案化和蚀刻，露出垫。保护性外涂层的其余部分用作掩模以去除覆盖在焊盘上的第二钝化层的部分。引线然后连接到焊盘，并且器件被封装以进行封装。第二钝化层在接合焊盘处与第一钝化层的边缘部分重叠以增强耐湿性。

6. 发明授权

US5696021A Method of making a field oxide isolation structure 失效
标题翻译：制作场氧化物隔离结构的方法
公开(公告)号：US5696021A
公开(公告)日：1997-12-09
申请号：US474537
申请日：1995-06-07
申请人： Tsiu Chiu Chan , Frank R. Bryant
发明人： Tsiu Chiu Chan , Frank R. Bryant
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76221
摘要： A method for creating isolation structures in a substrate without having to increase the field implant doses to prevent punch through. This particular advantage is achieved by first growing a pad oxide on the substrate. Polysilicon is deposited on top of the pad oxide layer. Next, silicon nitride, used for masking, is deposited on the polysilicon layer. An opening, also called an isolation space, is etched into the three layers, exposing part of the substrate. A first field oxide is grown in the opening. This first field oxide layer is etched to expose a portions of the substrate along the edge of the field oxide region. Then, trenches are etched into the exposed portions of the substrate, and field implantation of dopants is performed. After implantation, a second field oxide layer is grown. The silicon nitride, polysilicon, and pad oxide are then removed, resulting in the isolation structure of the present invention.
摘要翻译：一种用于在衬底中产生隔离结构而不必增加现场注入剂量以防止穿透的方法。通过首先在衬底上生长衬垫氧化物来实现这个特别的优点。多晶硅沉积在衬垫氧化物层的顶部。接下来，用于掩蔽的氮化硅沉积在多晶硅层上。还将一个开口（也称为隔离空间）蚀刻到三层中，使基板的一部分露出。在开口中生长第一场氧化物。蚀刻第一场氧化物层以沿着场氧化物区域的边缘露出衬底的一部分。然后，将沟槽蚀刻到衬底的暴露部分中，并进行掺杂剂的场注入。植入后，生长第二场氧化物层。然后去除氮化硅，多晶硅和衬垫氧化物，产生本发明的隔离结构。

7. 发明授权

US5489797A Local interconnect structure 失效
标题翻译：本地互连结构
公开(公告)号：US5489797A
公开(公告)日：1996-02-06
申请号：US420353
申请日：1995-04-11
申请人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
发明人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
IPC分类号： H01L21/768 , H01L23/532 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L27/1104 , H01L21/76895 , H01L23/53271 , H01L2924/0002 , Y10S257/903
摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
摘要翻译：互连结构及其形成方法适用于诸如SRAM器件的集成电路。该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

8. 发明授权

US5309025A Semiconductor bond pad structure and method 失效
标题翻译：半导体焊盘结构及方法
公开(公告)号：US5309025A
公开(公告)日：1994-05-03
申请号：US919949
申请日：1992-07-27
申请人： Frank R. Bryant , Fusen E. Chen
发明人： Frank R. Bryant , Fusen E. Chen
IPC分类号： H01L21/60 , H01L23/485 , H01L23/29 , H01L23/48 , H01L29/46 , H01L29/54
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0347 , H01L2224/04042 , H01L2224/05082 , H01L2224/05187 , H01L2224/05556 , H01L2224/05558 , H01L2224/05599 , H01L2224/05624 , H01L2224/05666 , H01L2224/05684 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/14
摘要： A method for forming an improved bonding pad structure. A bond pad structure is formed by depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and conductive layer are then patterned and etched to define a conductive region. In a preferred embodiment, the conductive region is formed in the shape of a grid. A second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.
摘要翻译：一种形成改进的焊盘结构的方法。通过在半导体器件的下面的区域上沉积阻挡层，然后在阻挡层上沉积第一导电层，形成接合焊盘结构。然后对阻挡层和导电层进行图案化和蚀刻以限定导电区域。在优选实施例中，导电区域形成为网格形状。第二导电层沉积在导电区域和暴露的下部区域的一部分上。第二导电层与下面的区域形成良好的粘合剂接触，从而防止粘结垫剥离。

9. 发明授权

US5256895A Pad oxide protect sealed interface isolation 失效
标题翻译：垫氧化物保护密封接口隔离
公开(公告)号：US5256895A
公开(公告)日：1993-10-26
申请号：US863519
申请日：1992-03-31
申请人： Frank R. Bryant , Yu-Pin Han , Fu-Tai Liou
发明人： Frank R. Bryant , Yu-Pin Han , Fu-Tai Liou
IPC分类号： H01L21/32 , H01L21/762 , H01L27/12 , H01L23/48 , H01L29/40
CPC分类号： H01L21/32 , H01L21/76205
摘要： Field oxide regions are formed between drive regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.
摘要翻译：通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的驱动区之间的场氧化物区域，打开这些层以暴露硅衬底的一部分，去除暴露的衬底的一层，在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。在如图1所示的那些场地氧化物埋在衬底中的那些结构中。如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

10. 发明授权

US5196909A Capacitor for DRAM cell 失效
标题翻译： DRAM单元电容器
公开(公告)号：US5196909A
公开(公告)日：1993-03-23
申请号：US697227
申请日：1991-05-07
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10817 , H01L28/40
摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.
摘要翻译：适用于DRAM存储单元的电容器由多层多晶硅组成。存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

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