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1. 发明申请

US20120123713A1 Control of Delivery of Current Through One or More Discharge Lamps 有权
标题翻译：通过一个或多个放电灯传递电流的控制
公开(公告)号：US20120123713A1
公开(公告)日：2012-05-17
申请号：US13355452
申请日：2012-01-20
申请人： Hubertus Notohamiprodjo , Radu Pitigoi-Aron
发明人： Hubertus Notohamiprodjo , Radu Pitigoi-Aron
IPC分类号： G06F19/00 , G01R19/04 , G01R19/25
CPC分类号： G01R19/25 , H05B41/2828 , H05B41/3927
摘要： Method to identify a current drawn by a fluorescent lamp in a circuit. Methods include receiving a voltage supplied to a fluorescent lamp drawing a current in response to the voltage, digitally sampling the voltage at a sampling frequency and associating a first time stamp with a voltage value representing one of a maximum or minimum value in observed voltage, receiving the current after receiving the voltage, digitally sampling the current at the sampling frequency and associating multiple second time stamps with a corresponding multiple current values, identifying a second time stamp, a difference between the first time stamp and the second time stamp being within a threshold, and identifying a current value associated with the second time stamp as the current drawn by the fluorescent lamp.
摘要翻译：识别由电路中的荧光灯吸取的电流的方法。方法包括接收提供给荧光灯的电压，其响应于电压抽取电流，以采样频率对电压进行数字采样，并将第一时间戳与表示观察电压中的最大值或最小值之一的电压值相关联，接收所述电流在接收到所述电压之后，以采样频率对所述电流进行数字采样，并将多个第二时间戳与相应的多个电流值相关联，识别第二时间戳，所述第一时间戳与所述第二时间戳之间的差在阈值内并且将与第二时间戳相关联的当前值识别为由荧光灯绘制的电流。

2. 发明授权

US07796594B2 Logical bridging system and method 有权
标题翻译：逻辑桥接系统和方法
公开(公告)号：US07796594B2
公开(公告)日：2010-09-14
申请号：US12030822
申请日：2008-02-13
申请人： David Melman , Nir Arad , Nafea Bshara
发明人： David Melman , Nir Arad , Nafea Bshara
IPC分类号： H04L12/28
CPC分类号： H04L45/04 , H04L12/46 , H04L12/4625 , H04L45/00 , H04L45/08 , H04L45/60 , H04L49/109 , H04L49/351
摘要： A system and method of extending a standard bridge to enable execution of logical bridging functionality are disclosed. In some implementations, a logical bridge may assign source logical port information to a data packet based on characteristics of the data packet, employ the source logical port information to learn the source address and to forward the data packet to a logical egress port, and map the logical egress port to a physical egress port at which the data packet is to be egressed. A tunnel interface may optionally be applied to a data packet upon egress.
摘要翻译：公开了一种扩展标准网桥以实现逻辑桥接功能的执行的系统和方法。在一些实现中，逻辑桥可以基于数据分组的特性将源逻辑端口信息分配给数据分组，使用源逻辑端口信息来学习源地址并将数据分组转发到逻辑出口端口，并且映射到出口数据包的物理出口端口的逻辑出口端口。隧道接口可以可选地在出口时应用于数据分组。

3. 发明申请

US20080189451A1 Magnetic disk controller and method 有权
标题翻译：磁盘控制器及方法
公开(公告)号：US20080189451A1
公开(公告)日：2008-08-07
申请号：US12012321
申请日：2008-02-01
申请人： Soichi Isono , Minoru Tsukada , Tomoki Oura , Koji Takahashi
发明人： Soichi Isono , Minoru Tsukada , Tomoki Oura , Koji Takahashi
IPC分类号： G06F3/00
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/0619 , G06F3/0656 , G06F3/0676 , G06F12/0866 , G11B20/10527 , G11B20/1833 , G11B2020/1062 , G11B2020/1843 , G11B2220/2516
摘要： Among other disclosed subject matter, a magnetic disk controller includes an interface that receives and transmits data to be written into a magnetic disk. The magnetic disk controller includes a first buffer and a second buffer each of which temporarily stores data that is to be written into at least one sector of the magnetic disk. The magnetic disk controller includes an encoding unit that encodes the data stored in any of the first buffer and the second buffer into data representing a signal to be applied to the magnetic disk. A data width M between the encoding unit and the first and second buffers is at least equal to twice a data width N between the interface and the first and second buffers.
摘要翻译：在其他公开的主题中，磁盘控制器包括接收并发送要写入磁盘的数据的接口。磁盘控制器包括第一缓冲器和第二缓冲器，每个缓冲器和第二缓冲器临时存储要写入到磁盘的至少一个扇区中的数据。磁盘控制器包括编码单元，其将存储在任何第一缓冲器和第二缓冲器中的数据编码成表示要施加到磁盘的信号的数据。编码单元与第一和第二缓冲器之间的数据宽度M至少等于接口与第一和第二缓冲器之间的数据宽度N的两倍。

4. 发明申请

US20080157195A1 GEOMETRY OF MOS DEVICE WITH LOW ON-RESISTANCE 有权
标题翻译：具有低电阻性的MOS器件的几何
公开(公告)号：US20080157195A1
公开(公告)日：2008-07-03
申请号：US11964696
申请日：2007-12-26
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336
CPC分类号： H01L27/0207 , H01L21/823437 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/41725 , H01L29/41758 , H01L29/4238 , H01L29/78 , H01L29/7835
摘要： A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
摘要翻译：在基板上形成的金属氧化物半导体（MOS）器件和形成MOS器件的方法。 MOS器件包括漏极区域，围绕漏极区域的栅极区域，围绕栅极区域和漏极区域布置的源极区域以及围绕栅极区域布置并分离源极区域的体区域。栅极区域围绕漏极区域形成环路。以这种方式，MOS器件的导通电阻（Ron）减小而不增加MOS器件的面积。

5. 发明申请

US20080037444A1 Ad-hoc simple configuration 有权
标题翻译：特别简单的配置
公开(公告)号：US20080037444A1
公开(公告)日：2008-02-14
申请号：US11800166
申请日：2007-05-04
申请人： Kapil Chhabra
发明人： Kapil Chhabra
IPC分类号： H04L12/28
CPC分类号： H04W52/0241 , H04W52/0222 , H04W52/0254 , H04W60/00 , H04W84/18 , Y02D70/142 , Y02D70/22
摘要： A protocol governing the operation of an ad-hoc WLAN enables each device in the WLAN to be configured as a registrar and/or an enrollee. Accordingly, each device is configurable to support both the registrar as well as enrollee modes of operations. In response to a time-driven user action, the device may be configured to enter into a registrar mode or an enrollee mode. While in the registrar mode, the device enters into an aggressive beaconing phase by setting its beacon contention window to a relatively very small value. The aggressive beaconing increases the probability of the discovery of the registrar by the enrollees. Optionally the device may prompt the user to select between a registrar and an enrollee mode of operation by displaying the option on an LCD panel.
摘要翻译：管理自组织WLAN的操作的协议使得WLAN中的每个设备被配置为注册器和/或登记者。因此，每个设备都可配置为支持注册器以及注册人操作模式。响应于时间驱动的用户操作，设备可以被配置为进入注册器模式或登记者模式。在注册器模式下，设备通过将其信标竞争窗口设置为相对非常小的值来进入激进的信标阶段。激进的信号增加了参与者发现注册商的可能性。可选地，设备可以通过在LCD面板上显示该选项来提示用户在注册器和登记者操作模式之间进行选择。

6. 发明授权

US07288845B2 Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits 有权
标题翻译：在集成电路中的底层有源器件，无源器件和/或介电层上制造引线接合焊盘
公开(公告)号：US07288845B2
公开(公告)日：2007-10-30
申请号：US10434524
申请日：2003-05-08
申请人： Sehat Sutardja , Albert Wu , Jin-Yuan Lee , Mou-Shiung Lin
发明人： Sehat Sutardja , Albert Wu , Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/85399 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/04953 , H01L2924/00
摘要： A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.
摘要翻译：用于集成电路（IC）管芯的导线连接结构包括具有有源器件和/或无源器件的半导体晶片。一个或多个电介质层被布置为与有源和/或无源器件相邻。一个或多个金属互连层布置成与有源和/或无源器件相邻。接触垫布置在最外侧金属互连层中。钝化层布置在最外金属互连层上方，并且包括暴露接触焊盘的至少一个钝化开口。焊接层布置在钝化层和有源和/或无源器件上方，并通过钝化开口连接到接触焊盘。接合焊盘的形成不会损坏有源和/或无源器件。

7. 发明申请

US20070024385A1 Low-noise high-stability crystal oscillator 有权
公开(公告)号：US20070024385A1
公开(公告)日：2007-02-01
申请号：US11242621
申请日：2005-10-03
申请人： Jody Greenberg
发明人： Jody Greenberg
IPC分类号： H03B5/32
CPC分类号： H03L5/00 , H03B5/364
摘要： Circuits, methods, and apparatus that provide low-noise, high-stability crystal oscillators having controlled-amplitude differential output signals and DC level control. A crystal oscillator circuit has two feedback loops, one for setting the DC level of its signals, the other for adjusting the amplitude of those signals. The DC level feedback loop can set the DC component of the oscillator signals to a voltage midway between two supply voltages. The amplitude control loop sets the amplitude of the output of the crystal oscillator signal to be within a range. The amplitude can be set to provide a maximum swing without clipping the supply voltages in order to provide high-stability and minimal jitter. The amplitude control circuit can also be digital for improved noise performance. The time constants of these two loops can be separated such that instabilities are avoided.

8. 发明授权

US10447823B2 Packet parsing engine 有权
公开(公告)号：US10447823B2
公开(公告)日：2019-10-15
申请号：US14150622
申请日：2014-01-08
申请人： CAVIUM, LLC
发明人： Wilson Parkhurst Snyder, II , Daniel Adam Katz , Varada Ramesh Ogale
IPC分类号： H04L29/06 , G06F9/38 , G06F9/50
摘要： A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

9. 发明授权

US09641127B1 Operational transconductance amplifier of improved linearity 有权
公开(公告)号：US09641127B1
公开(公告)日：2017-05-02
申请号：US14731194
申请日：2015-06-04
申请人： Marvell International Ltd.
发明人： Zhigang Xu , Junxiong Deng , Taotao Yan
IPC分类号： H03F3/26 , H03F1/02 , H03F3/45 , H04B10/50 , H04B10/564
CPC分类号： H04B10/564 , H03F1/3211 , H03F3/45188 , H03F3/45475 , H03F2203/45116 , H04B10/501
摘要： Aspects of the disclosure provide an operational transconductance amplifier (OTA) having an output stage. The output stage includes a first amplifier path configured to drive a first output current from a first power supply and a first resistor coupled between the first power supply and a source terminal of a first transistor in the first amplifier path. The first resistor is configured to improve a linearity of the OTA.

10. 发明申请

US20130154743A1 CLASS AB AMPLIFIERS 有权
标题翻译： AB类放大器
公开(公告)号：US20130154743A1
公开(公告)日：2013-06-20
申请号：US13769700
申请日：2013-02-18
申请人： Marvell Semiconductor Inc.
发明人： Sehat Sutardja , Farbod Aram
IPC分类号： H03F3/26
CPC分类号： H03F3/265 , H03F3/191 , H03F3/211 , H03F2203/21131
摘要： An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load.
摘要翻译：放大器包括第一开关和第二开关，每个具有第一端子和第二端子。第一和第二开关的第一端子分别与第一储能电路和第二储能电路连通。第二开关的第二端子与第一开关的第二端子通信。第一电容，其具有直接连接到（i）第一开关的第二端子的第一端子和（ii）第二开关的第二端子。第一电容的第二端子直接连接到放大器的第一输入电压。第一负载跨越（i）第一开关的第一端子和（ii）第二开关的第一端子连接。放大器在第一个负载上产生第一个输出。

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