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1. 发明授权

US07955936B2 Semiconductor fabrication process including an SiGe rework method 有权
标题翻译：半导体制造工艺包括SiGe返工方法
公开(公告)号：US07955936B2
公开(公告)日：2011-06-07
申请号：US12172756
申请日：2008-07-14
申请人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
发明人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/30608 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.
摘要翻译：一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

2. 发明申请

US20150317473A1 DEVICE AND ACCESSORY PAIRING 有权
标题翻译：设备和配件配对
公开(公告)号：US20150317473A1
公开(公告)日：2015-11-05
申请号：US14266691
申请日：2014-04-30
申请人： Infineon Technologies Austria AG
发明人： Cheow Guan Lim , Robert P. Rozario
IPC分类号： G06F21/44
CPC分类号： G06F21/445 , G06F21/44 , G06F2221/2129
摘要： A device authenticates accessories by detecting that an accessory is attached to the device, determining a unique identification (ID) for the accessory, determining, based on the unique ID, if the accessory has been paired to the device, and in response to determining that the accessory has been paired to the device, enable use of the accessory by the device. In response to determining the accessory has not been paired to the device, the devices performs a secondary authentication process on the accessory.
摘要翻译：设备通过检测附件附接到设备来认证附件，确定附件的唯一标识（ID），基于唯一ID确定附件是否已经与设备配对，以及响应于确定配件已配对设备，使设备可以使用附件。响应于确定附件未与设备配对，设备对附件执行二次认证处理。

3. 发明申请

US20150280696A1 CIRCUIT FOR COMMON MODE REMOVAL FOR DC-COUPLED FRONT-END CIRCUITS 有权
标题翻译：用于直流耦合前端电路的通用模式拆除电路
公开(公告)号：US20150280696A1
公开(公告)日：2015-10-01
申请号：US14225003
申请日：2014-03-25
申请人： Infineon Technologies Austria AG
发明人： Giuseppe Bernacchia , Cha-fu Tsai
IPC分类号： H03K5/007
CPC分类号： H03K5/007
摘要： In one example, a method includes receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first differential signal includes a first common mode voltage; receiving a second common mode voltage. The method further includes determining, by a circuit, a second differential signal including a third voltage signal and a fourth voltage signal, wherein a difference between the third voltage signal and the fourth voltage signal is based on a difference between the first voltage signal and the second voltage signal, wherein the second differential signal includes the second common mode voltage. The method further includes outputting, substantially continuously, the second differential signal.
摘要翻译：在一个示例中，一种方法包括接收包括第一电压信号和第二电压信号的第一差分信号，其中第一差分信号包括第一共模电压; 接收第二共模电压。该方法还包括通过电路确定包括第三电压信号和第四电压信号的第二差分信号，其中第三电压信号和第四电压信号之间的差是基于第一电压信号和第四电压信号之间的差值第二电压信号，其中第二差分信号包括第二共模电压。该方法还包括基本连续地输出第二差分信号。

4. 发明授权

US08822342B2 Method to reduce depth delta between dense and wide features in dual damascene structures 有权
标题翻译：减少双重镶嵌结构密集和宽特征之间深度三角洲的方法
公开(公告)号：US08822342B2
公开(公告)日：2014-09-02
申请号：US12981519
申请日：2010-12-30
申请人： Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
发明人： Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76813 , H01L21/31144 , H01L21/76808 , H01L21/76814 , H01L2221/1036 , H01L2221/1063
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
摘要翻译：公开了一种形成装置的方法。该方法包括提供用具有第一和第二区域的电介质层制备的衬底。第一区域包括宽的特征，第二区域包括狭窄的特征。在宽和窄特征的底部之间存在深度增量。在基板上形成非保形层，并且在第一和第二区域中对宽且窄的沟槽进行排列。去除非保形层。去除非保形层减少了第一和第二区域中宽和窄特征的底部之间的深度增量。

5. 发明申请

US20140153295A1 Buck-Flyback Converter 有权
标题翻译：降压反激式转换器
公开(公告)号：US20140153295A1
公开(公告)日：2014-06-05
申请号：US13690388
申请日：2012-11-30
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： Mladen Ivankovic , Fred Sawyer
IPC分类号： H02M3/335
CPC分类号： H02M3/3353 , H02M3/33507 , H02M3/33523 , H02M3/3372 , H02M3/3378 , Y02B70/1433
摘要： A two-transistor flyback converter includes a transformer having a primary side and a secondary side, a first transistor connected between an input voltage source and a first terminal of the primary side, a second transistor connected between ground and a second terminal of the primary side, and a diode directly connected between the first terminal of the primary side and ground. The first and second transistors are operable to switch on and off simultaneously and with no current return from the primary side to the input voltage source when the input voltage source is less than a reflected voltage from the secondary side.
摘要翻译：双晶体管反激转换器包括具有初级侧和次级侧的变压器，连接在初级侧的输入电压源和第一端子之间的第一晶体管，连接在地与第一侧的第二端子之间的第二晶体管以及直接连接在初级侧的第一端子和地之间的二极管。当输入电压源小于来自次级侧的反射电压时，第一和第二晶体管可操作以同时接通和断开，并且没有电流从初级侧返回到输入电压源。

6. 发明申请

US20140118070A1 Doherty Amplifier Circuit with Phase-Controlled Load Modulation 有权
标题翻译：带相位控制负载调制的多赫蒂放大器电路
公开(公告)号：US20140118070A1
公开(公告)日：2014-05-01
申请号：US13665321
申请日：2012-10-31
申请人： Infineon Technologies North America Corp.
发明人： Richard Wilson , Saurabh Goel
IPC分类号： H03F3/66 , H03F3/189
CPC分类号： H03F3/601 , H03F1/0288 , H03F1/56
摘要： A symmetric Doherty amplifier includes a main amplifier and a peaking amplifier of the same size as the main amplifier. The symmetric Doherty amplifier is configured to operate at peak output power when the main amplifier and the peaking amplifier are each in saturation, and at output-back-off (OBO) when the main amplifier is in saturation and the peaking amplifier is not in saturation. Phase shift circuitry is configured to shift the phase at an output of the peaking amplifier at OBO so that a load impedance seen by the main amplifier and efficiency of the symmetric Doherty amplifier both increase at OBO as a function of the phase shift at the peaking amplifier output.
摘要翻译：对称Doherty放大器包括与主放大器相同尺寸的主放大器和峰值放大器。当主放大器和峰化放大器均处于饱和状态时，对称Doherty放大器配置为以峰值输出功率工作，当主放大器处于饱和状态时，输出回退（OBO）和峰值放大器不饱和。相移电路被配置为在OBO的偏移放大器的输出处移位相位，使得由主放大器看到的负载阻抗和对称Doherty放大器的效率在OBO处都随着峰值放大器处的相移而增加输出。

7. 发明申请

US20130241639A1 IMPEDANCE SPREADING WIDEBAND DOHERTY AMPLIFIER CIRCUIT WITH PEAKING IMPEDANCE ABSORPTION 有权
标题翻译：阻抗扩展宽带放大器放大器电路，具有突出阻抗吸收
公开(公告)号：US20130241639A1
公开(公告)日：2013-09-19
申请号：US13422938
申请日：2012-03-16
申请人： Richard Wilson , Saurabh Goel
发明人： Richard Wilson , Saurabh Goel
IPC分类号： H03F3/68
CPC分类号： H03F1/0288
摘要： A wideband Doherty amplifier circuit includes a main amplifier configured to operate in a linear mode, a peaking amplifier configured to operate in a non-linear mode and a Doherty combiner directly connected to an output of each amplifier so that no output match devices are in the path between the amplifier outputs and the Doherty combiner. The Doherty combiner is configured to present the same load impedance to each amplifier when both amplifiers are conducting and present a modulated load impedance to the main amplifier when the peaking amplifier is non-conducting so that a variation in the VSWR seen by the main amplifier is less than 5% over a plurality of frequency bands and/or so that the peaking amplifier has an off-state impedance spreading of 20 degrees or less over the plurality of frequency bands.
摘要翻译：宽带Doherty放大器电路包括被配置为以线性模式操作的主放大器，被配置为以非线性模式操作的峰值放大器和直接连接到每个放大器的输出的Doherty组合器，使得没有输出匹配器件位于放大器输出和Doherty组合器之间的路径。 Doherty组合器被配置为当两个放大器导通时向每个放大器呈现相同的负载阻抗，并且当峰值放大器不导通时，向主放大器呈现调制负载阻抗，使得主放大器看到的VSWR的变化为在多个频带中小于5％和/或使得峰化放大器在多个频带上具有20度或更小的截止状态阻抗扩展。

8. 发明申请

US20120319780A1 WIDEBAND DOHERTY AMPLIFIER CIRCUIT HAVING A CONSTANT IMPEDANCE COMBINER 有权
标题翻译：具有恒定阻抗组合的宽带DOHERTY放大器电路
公开(公告)号：US20120319780A1
公开(公告)日：2012-12-20
申请号：US13163388
申请日：2011-06-17
申请人： Richard Wilson , Saurabh Goel
发明人： Richard Wilson , Saurabh Goel
IPC分类号： H03F3/68
CPC分类号： H03F3/604 , H03F1/0288 , H03F1/56 , H03F2200/318 , H03F2200/387 , H03F2200/408
摘要： A three way wideband Doherty amplifier circuit includes a first peaking amplifier operable to turn on at a first power level, a second peaking amplifier operable to turn on at a second power level below the first power level and a main power amplifier operable to turn on at all power levels. The main power amplifier has a high impedance load modulated state when the first and second peaking amplifiers are turned off. The three way wideband Doherty amplifier circuit further includes a constant impedance combiner connected to an output of each amplifier. The constant impedance combiner has a characteristic impedance which matches the impedance of the main amplifier in the high impedance load modulated state with or without an output matching device connecting the main amplifier output to the constant impedance combiner, as viewed from the output of the main amplifier.
摘要翻译：三路宽带Doherty放大器电路包括可操作以在第一功率电平导通的第一峰化放大器，可操作以在低于第一功率电平的第二功率电平下导通的第二峰化放大器和可操作以在所有功率级别。当第一和第二峰值放大器关闭时，主功率放大器具有高阻抗负载调制状态。三路宽带Doherty放大器电路还包括连接到每个放大器的输出的恒定阻抗组合器。恒定阻抗组合器具有与主放大器在高阻抗负载调制状态下的阻抗匹配的特性阻抗，具有或不具有将主放大器输出连接到恒定阻抗组合器的输出匹配装置，从主放大器的输出。

9. 发明申请

US20120168957A1 METHOD TO REDUCE DEPTH DELTA BETWEEN DENSE AND WIDE FEATURES IN DUAL DAMASCENE STRUCTURES 有权
标题翻译：降低DASASCENE结构中DENSE和WIDE特征之间深度差的方法
公开(公告)号：US20120168957A1
公开(公告)日：2012-07-05
申请号：US12981519
申请日：2010-12-30
申请人： Ravi Prakash SRIVASTAVA , Oluwafemi O. OGUNSOLA , Craig CHILD , Muhammed Shafi Kurikka Valappil PALLACHALIL , Habib HICHRI , Matthew ANGYAL , Hideshi MIYAJIMA
发明人： Ravi Prakash SRIVASTAVA , Oluwafemi O. OGUNSOLA , Craig CHILD , Muhammed Shafi Kurikka Valappil PALLACHALIL , Habib HICHRI , Matthew ANGYAL , Hideshi MIYAJIMA
IPC分类号： H01L23/48 , H01L21/31 , H01L21/28
CPC分类号： H01L21/76813 , H01L21/31144 , H01L21/76808 , H01L21/76814 , H01L2221/1036 , H01L2221/1063
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
摘要翻译：公开了一种形成装置的方法。该方法包括提供用具有第一和第二区域的电介质层制备的衬底。第一区域包括宽的特征，第二区域包括狭窄的特征。在宽和窄特征的底部之间存在深度增量。在基板上形成非保形层，并且在第一和第二区域中对宽且窄的沟槽进行排列。去除非保形层。去除非保形层减少了第一和第二区域中宽和窄特征的底部之间的深度增量。

10. 发明申请

US20120068691A1 di/dt Current Sensing 有权
标题翻译： di / dt电流检测
公开(公告)号：US20120068691A1
公开(公告)日：2012-03-22
申请号：US12887835
申请日：2010-09-22
申请人： Jens Ejury
发明人： Jens Ejury
IPC分类号： G01R11/00 , H01L21/00
CPC分类号： H02M1/00 , G01R15/181 , G01R19/0092 , H01F19/04 , H01L2924/0002 , H02M2001/0009 , Y10T29/41 , H01L2924/00
摘要： A circuit includes a power circuit and a current sensing circuit. The power circuit has a main current loop. The current sensing circuit is spaced apart from and electrically decoupled from the power circuit. The current sensing circuit is operable to generate a voltage proportional to an electromagnetic field generated responsive to a current change in the main current loop of the power circuit and generate a current information signal based on the voltage. The current information signal describes the current in the main current loop.
摘要翻译：电路包括电源电路和电流检测电路。电源电路有一个主电流回路。电流感测电路与电源电路间隔开并与电源电耦合。电流感测电路可操作以产生与响应于电力电路的主电流回路中的电流变化产生的电磁场成比例的电压，并且基于该电压产生电流信息信号。当前信息信号描述主电流回路中的电流。

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