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1. 发明授权

US10560086B2 Fault and short-circuit protected output driver 有权
公开(公告)号：US10560086B2
公开(公告)日：2020-02-11
申请号：US15903690
申请日：2018-02-23
申请人： Infineon Technologies North America Corp.
发明人： Andre Mourrier , Vincent Thiery , Vincent Laville , Loic Bourguine
IPC分类号： H03K17/082 , H02H7/08 , H02H7/122 , H02H3/08 , H02H3/20 , H02M7/5387 , H03K17/284 , H02H3/087
摘要： A driver and protection circuit for driving a power switch is disclosed. The driver and protection circuit includes a fault detection block configured to detect a discrepancy between a reference drive signal and a measured voltage at a gate of the power switch. The driver and protection circuit also includes a short circuit detection block configured to detect a gate-to-source short circuit or a gate-to-drain short circuit of the power switch. The driver and protection circuit further includes a latch coupled to the fault detection block and the short circuit detection block to selectively turn off an output driver coupled to the gate of the power switch when a fault or a short circuit is detected, and wherein the latch is configured to send a diagnostic signal when the fault or the short circuit is detected.

2. 发明申请

US20150123208A1 Transformer Input Matched Transistor 有权
标题翻译：变压器输入匹配晶体管
公开(公告)号：US20150123208A1
公开(公告)日：2015-05-07
申请号：US14069867
申请日：2013-11-01
申请人： Infineon Technologies North America Corp.
发明人： Marvin Marbell , EJ Hashimoto
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6644 , H01L2223/665 , H01L2224/48091 , H01L2224/48137 , H01L2224/4903 , H01L2224/49111 , H01L2224/49175 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2924/3011 , H01L2924/30111 , H03F3/193 , H03F2200/534 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An RF power transistor package includes an input lead, an output lead, and an RF power transistor having a gate, a drain and a defined gain over an RF frequency range for which the RF power transistor is configured to operate. The RF power transistor package further includes a transformer electrically isolating and inductively coupling the gate of the RF power transistor to the input lead. The transformer is configured to block signals below the RF frequency range of the RF power transistor and pass signals within the RF frequency range of the RF power transistor. The RF power transistor package also includes a DC feed terminal for providing DC bias to the gate of the RF power transistor.
摘要翻译： RF功率晶体管封装包括输入引线，输出引线和RF功率晶体管，RF功率晶体管具有在RF功率晶体管被配置为工作的RF频率范围上的栅极，漏极和限定的增益。 RF功率晶体管封装还包括将RF功率晶体管的栅极电耦合到电感耦合到输入引线的变压器。变压器被配置为阻挡在RF功率晶体管的RF频率范围之下的信号，并且在RF功率晶体管的RF频率范围内传递信号。 RF功率晶体管封装还包括用于向RF功率晶体管的栅极提供DC偏置的DC馈电端子。

3. 发明申请

US20140167634A1 Method and Circuit for LED Driver Dimming 有权
标题翻译： LED驱动器调光方法与电路
公开(公告)号：US20140167634A1
公开(公告)日：2014-06-19
申请号：US13716677
申请日：2012-12-17
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： Mladen Ivankovic , Fred Sawyer
IPC分类号： H05B37/02
CPC分类号： H05B33/0851 , H05B33/0815 , Y02B20/347
摘要： An LED driver includes a transformer, current control loop and current adjustment circuit. The primary side of the transformer transfers energy to the secondary side of the transformer responsive to an input signal. The secondary side delivers output current to one or more LEDs at a magnitude corresponding to the amount of energy transferred to the secondary side. The current control loop controls current in the primary side so that the output current equals a reference current signal. The current adjustment circuit injects a current adjustment signal into the current control loop responsive to a phase-cut signal which removes a portion of the input signal. The current control loop also decreases the current in the primary side responsive to the current adjustment signal so that a brightness of each LED connected to the secondary side is decreased by an amount corresponding to the magnitude of the current adjustment signal.
摘要翻译： LED驱动器包括变压器，电流控制回路和电流调节电路。变压器的初级侧根据输入信号将能量传递到变压器的次级侧。次级侧以对应于传输到次级侧的能量的量的大小向一个或多个LED提供输出电流。电流控制环路控制初级侧的电流，使输出电流等于参考电流信号。电流调节电路响应于消除输入信号的一部分的相位切断信号将电流调节信号注入电流控制环路。响应于当前调整信号，电流控制回路还减小初级侧的电流，使得连接到次级侧的每个LED的亮度减小与当前调节信号的幅度相对应的量。

4. 发明申请

US20040256675A1 Electro-static discharge protection circuit and method for making the same 失效
标题翻译：静电放电保护电路及其制作方法
公开(公告)号：US20040256675A1
公开(公告)日：2004-12-23
申请号：US10464382
申请日：2003-06-17
申请人： Infineon Technologies North America Corp.
发明人： Grant McNeil
IPC分类号： H01L023/62
CPC分类号： H01L27/0255 , H01L27/10841 , H01L27/10897
摘要： As disclosed herein, an electrostatic discharge (ESD) protection circuit is provided for an integrated circuit including a semiconductor substrate. The ESD protection circuit includes a plurality of active devices formed in the semiconductor substrate, the active devices being formed by a process including a plurality of steps carried out to form, at the same time, a plurality of active devices having a function other than ESD protection. For example, the ESD circuit may include an array of vertical transistors formed according to a process including many of the steps used to form, at the same time, vertical transistors of a DRAM array. Also disclosed is the formation of an ESD circuit in an nullunusablenull area of a semiconductor chip, such as under a bond pad, land or under bump metallization of the chip.
摘要翻译：如本文所公开的，为包括半导体衬底的集成电路提供了静电放电（ESD）保护电路。 ESD保护电路包括形成在半导体衬底中的多个有源器件，有源器件通过包括多个步骤的处理形成，同时形成具有除了ESD之外的功能的多个有源器件保护。例如，ESD电路可以包括根据包括用于同时形成DRAM阵列的垂直晶体管的许多步骤的工艺形成的垂直晶体管阵列。还公开了在半导体芯片的“不可用”区域中形成ESD电路，例如在焊盘下方，芯片的焊盘或凸块下方金属化。

5. 发明申请

US20040241939A1 METHOD OF FORMING A COLLAR USING SELECTIVE SiGe/AMORPHOUS Si ETCH 失效
标题翻译：使用选择性SiGe /无定形Si ETCH形成胶束的方法
公开(公告)号：US20040241939A1
公开(公告)日：2004-12-02
申请号：US10250046
申请日：2003-05-30
申请人： International Business Machines Corporation , Infineon Technologies North America Corp.
发明人： Jochen Beintner , Naim Moumen , Porshia S. Wrschka
IPC分类号： H01L021/8242 , H01L021/20 , H01L021/461
CPC分类号： H01L27/1087 , H01L21/30604 , H01L29/66181 , H01L29/945
摘要： A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.
摘要翻译：提供了一种形成沟槽存储单元结构的套环隔离的方法，其中首先将非晶硅（a：Si）和硅锗（SiGe）形成沟槽结构。与SiGe相比，对a：Si有选择性的蚀刻工艺用于限定将形成套环隔离的区域。在本发明中采用的选择性蚀刻工艺是湿法蚀刻工艺，其包括用HF蚀刻，漂洗，用NH 4 OH蚀刻，漂洗和用一元醇如异丙醇干燥。 NH 4 OH蚀刻和漂洗的顺序可以重复任意次数。在本发明的选择性蚀刻工艺中使用的条件能够以比SiGe更快的速度蚀刻Si。

6. 发明申请

US20040238919A1 Methods and apparatus for providing an antifuse function 有权
标题翻译：提供反熔丝功能的方法和装置
公开(公告)号：US20040238919A1
公开(公告)日：2004-12-02
申请号：US10447018
申请日：2003-05-28
申请人： Infineon Technologies North America Corp. , International Business Machines Corporation
发明人： Axel Brintzinger , Carl Radens , William Tonti
IPC分类号： H01L021/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.
摘要翻译：公开了用于提供反熔丝的方法和装置，其中反熔丝包括具有由浅沟槽隔离（STI）边界限定的有源区的半导体衬底; 栅极导体，其设置在所述半导体衬底上方并且覆盖所述STI边界的至少一部分; 设置在所述半导体衬底和所述栅极导体之间的电介质; 耦合到所述栅极导体的第一端子; 以及耦合到所述半导体衬底的第二端子，其中所述电介质的击穿导致所述栅极导体的区域和所述有源区域的区域之间的电连接包括基本上靠近所述STI边界。

7. 发明申请

US20040224451A1 DUAL GATE MATERIAL PROCESS FOR CMOS TECHNOLOGIES 失效
标题翻译： CMOS技术的双栅材料工艺
公开(公告)号：US20040224451A1
公开(公告)日：2004-11-11
申请号：US10249800
申请日：2003-05-08
申请人： International Business Machines Corporation , Infineon Technologies North America Corp
发明人： Jia Chen , Andreas E. Grassmann
IPC分类号： H01L021/8238
CPC分类号： H01L21/823842
摘要： A method and structure for a method of manufacturing a device having different types of transistors, wherein gates of the different types of transistors in the device comprise different materials. The method comprises depositing a silicon layer on a gate dielectric layer, depositing a first-type gate material on the silicon layer, removing the first-type gate material from areas where a second-type gate is to be formed, depositing a second-type gate material on the silicon layer in areas where the first-type gate material was removed, and simultaneously patterning the first-type gate material and the second-type gate material into first-type and second-type gates, and anneal and transform the two types of gate materials.
摘要翻译：用于制造具有不同类型晶体管的器件的方法的方法和结构，其中器件中不同类型的晶体管的栅极包括不同的材料。该方法包括在栅极电介质层上沉积硅层，在硅层上沉积第一种类型的栅极材料，从要形成第二类型栅极的区域去除第一种类型的栅极材料; 在去除了第一种类型的栅极材料的区域中的硅层上的栅极材料，同时将第一种栅极材料和第二种栅极材料构图成第一类型和第二种栅极，并且对两种栅极材料进行退火和变换门材料种类。

8. 发明申请

US20040197984A1 Adhesion layer for Pt on SiO2 审中-公开
公开(公告)号：US20040197984A1
公开(公告)日：2004-10-07
申请号：US10803363
申请日：2004-03-17
申请人： Infineon Technologies North America Corp. , International Business Machines Corp.
发明人： Jingyu Lian , Kwong Hon Wong , Michael Wise , Young Limb , Nicolas Nagel
IPC分类号： H01L021/8242
CPC分类号： H01L28/65 , Y10T428/12597 , Y10T428/12875
摘要： Si, Al, Al plus TiN, and Ir02 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (5i02) substrate in capacitor structures of memory devices.

9. 发明申请

US20040175921A1 Reduction of the shear stress in copper via's in organic interlayer dielectric material 有权
标题翻译：在有机层间介质材料中减少铜通道中的剪切应力
公开(公告)号：US20040175921A1
公开(公告)日：2004-09-09
申请号：US10379346
申请日：2003-03-04
申请人： Infineon Technologies North America Corp.
发明人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
IPC分类号： H01L021/4763
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.
摘要翻译：在包含逻辑电路（微处理器，Asics或其他）或随机存取存储器单元（DRAMS）的半导体主体上的互连层形成为以显着减少相邻导体/通孔之间的短路数， 0.18微米或更小。这是通过蚀刻完成的，以在化学机械抛光工艺完成后在每一层上形成凹陷的铜顶表面。在凹陷的铜表面上施加的阻挡层的厚度被控制成与周围的绝缘体表面基本上共面。较厚的阻挡层消除了对覆盖层的需要。消除覆盖层导致整体电容耦合，应力和成本的降低。

10. 发明申请

US20040150423A1 Voltage down converter for low voltage operation 有权
标题翻译：降压转换器用于低电压工作
公开(公告)号：US20040150423A1
公开(公告)日：2004-08-05
申请号：US10358581
申请日：2003-02-05
申请人： Infineon Technologies North America Corp.
发明人： Jungwon Suh
IPC分类号： H03K019/0175
CPC分类号： H03K19/018578
摘要： A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage generator that produces a reference voltage corresponding to the value of the internal voltage, a comparator having opposite polarity inputs for producing an amplified output control signal, and a pull-up device operating from the external voltage that receives the control signal from the comparator to produce the internal voltage as an input. A dual source follower is located between the reference voltage generator and comparator and has two sections having cross-coupled inputs which respectively receive the internal reference voltage and the internal voltage to produce output voltages moving in opposite directions, each of which is applied to one input of the comparator, thereby translating the difference between Vintref and Vint to a level in a range that can be better amplified by the comparator.
摘要翻译：用于将外部电压转换为器件的较低值内部电压的半导体存储器件的降压转换器具有产生与内部电压值相对应的参考电压的电压发生器，具有相反极性输入的比较器，用于产生放大的输出控制信号和从外部电压工作的上拉装置，其接收来自比较器的控制信号以产生内部电压作为输入。双源极跟随器位于参考电压发生器和比较器之间，并且具有两个部分，其交叉耦合输入分别接收内部参考电压和内部电压，以产生沿相反方向移动的输出电压，每个输入电压施加到一个输入端的比较器，从而将Vintref和Vint之间的差异转换为可以被比较器更好地放大的范围内的电平。

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