专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09899474B2 Nanotube semiconductor devices 有权
公开(公告)号：US09899474B2
公开(公告)日：2018-02-20
申请号：US15617342
申请日：2017-06-08
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07 , H01L29/74 , H01L31/111 , H01L29/08 , H01L29/66 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/872 , H01L21/265 , H01L27/06 , H01L29/06 , H01L29/10
CPC分类号： H01L29/0886 , H01L21/26586 , H01L27/0623 , H01L27/0629 , H01L27/0664 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0676 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/36 , H01L29/365 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/41775 , H01L29/4236 , H01L29/42368 , H01L29/66136 , H01L29/66143 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/861 , H01L29/8613 , H01L29/872 , H01L29/8725
摘要： Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.

2. 发明授权

US09147674B2 Closed cell configuration to increase channel density for sub-micron planar semiconductor power device 有权
标题翻译：闭孔配置，以增加亚微米平面半导体功率器件的通道密度
公开(公告)号：US09147674B2
公开(公告)日：2015-09-29
申请号：US13134407
申请日：2011-06-06
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： H01L27/02 , H01L29/423 , H01L23/528 , H01L23/535 , H01L23/52 , H01L27/088
CPC分类号： H01L29/41758 , H01L23/52 , H01L23/528 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L29/0696 , H01L29/4238 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
摘要翻译：一种半导体功率器件，其支撑在包括多个晶体管单元的半导体衬底上，每个单元具有设置在半导体衬底中的栅极区域的相对侧上的源极和漏极区域。在栅极区域的顶部形成栅电极作为电极层，用于控制在源区和漏区之间传输的电流。设置在半导体衬底顶部的栅极电极层被图案化成波状条纹，用于基本上增加跨越栅极的源极和漏极区域之间的电流传导区域。

3. 发明授权

US08563360B2 Power semiconductor device package and fabrication method 有权
标题翻译：功率半导体器件封装及制造方法
公开(公告)号：US08563360B2
公开(公告)日：2013-10-22
申请号：US12479995
申请日：2009-06-08
申请人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
发明人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
IPC分类号： H01L21/00
CPC分类号： H01L23/492 , H01L23/04 , H01L24/37 , H01L24/40 , H01L25/072 , H01L29/0657 , H01L2224/37011 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/73253 , H01L2224/84801 , H01L2224/8485 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/12044 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/83 , H01L2224/37099
摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.
摘要翻译：功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

4. 发明授权

US08558276B2 Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) 有权
标题翻译：底部源NMOS触发齐纳钳位用于配置超低电压瞬态电压抑制器（TVS）
公开(公告)号：US08558276B2
公开(公告)日：2013-10-15
申请号：US12456555
申请日：2009-06-17
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L29/02
CPC分类号： H01L27/0266 , H01L29/732
摘要： A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal. The gate may be shorted to the drain for configuring the BS-MOSFET transistor into a two terminal device with a gate-to-source voltage equal to a drain-to-source voltage. The drain/collector/cathode terminal disposed on top of the trench gate turns on the BS-MOSFET upon application of a threshold voltage of the BS-MOSFET thus triggering the bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of the BS-MOSFET.
摘要翻译：支持在其上支撑外延层的半导体衬底上的低电压瞬变电压抑制（TVS）器件。 TVS器件还包括底源金属氧化物半导体场效应晶体管（BS-MOSFET），其包括被包围在设置在半导体衬底的顶表面附近的体区中的漏极区域围绕的沟槽栅极，其中漏极区域与构成结二极管的主体区域和包含在构成双极晶体管的外延层顶部的主体区域中的漏极区域，其中顶部电极设置在用作漏极/集电极端子的半导体的顶表面上，并且底部电极设置在用作源/发射极的半导体衬底的底表面。主体区域还包括电连接到主体到源短路连接的表面体接触区域，从而将身体区域连接到用作源极/发射极端子的底部电极。栅极可能短路到漏极，用于将BS-MOSFET晶体管配置为栅极至源极电压等于漏极 - 源极电压的双端子器件。设置在沟槽栅极顶部的漏极/集电极/阴极端子在施加BS-MOSFET的阈值电压时导通BS-MOSFET，因此触发双极晶体管用于钳位和抑制基本接近阈值电压的瞬态电压 BS-MOSFET。

5. 发明申请

US20130075746A1 Lateral PNP Bipolar Transistor with Narrow Trench Emitter 有权
标题翻译：具有窄沟槽发射极的横向PNP双极晶体管
公开(公告)号：US20130075746A1
公开(公告)日：2013-03-28
申请号：US13242970
申请日：2011-09-23
申请人： Shekar Mallikarjunaswamy , François Hébert
发明人： Shekar Mallikarjunaswamy , François Hébert
IPC分类号： H01L29/04 , H01L21/331
CPC分类号： H01L29/6625 , H01L21/02532 , H01L21/02595 , H01L21/2254 , H01L21/31111 , H01L21/324 , H01L21/76224 , H01L29/0649 , H01L29/0808 , H01L29/735
摘要： A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
摘要翻译：横向双极晶体管包括沟槽发射极和沟槽集电极区域，以形成超窄的发射极区域，从而提高发射极效率。使用相同的沟槽工艺来形成发射极/集电极沟槽以及沟槽隔离结构，使得不需要额外的处理步骤来形成沟槽发射极和集电极。在本发明的实施例中，可以使用离子注入形成在半导体层中的沟槽中形成沟槽发射极和沟槽集电极区域。在其他实施例中，沟槽发射极和沟槽集电极区域可以通过从重掺杂的多晶硅填充的沟槽中的掺杂剂的扩散而形成。

6. 发明申请

US20120205737A1 SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION 有权
标题翻译： SHIELDED GATE TRENCH MOSFET器件和制造
公开(公告)号：US20120205737A1
公开(公告)日：2012-08-16
申请号：US13456406
申请日：2012-04-26
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

7. 发明授权

US08193580B2 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US08193580B2
公开(公告)日：2012-06-05
申请号：US12583191
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

8. 发明授权

US08098466B2 Circuit configurations to reduce snapback of a transient voltage suppressor 有权
标题翻译：电路配置，以减少瞬态电压抑制器的快速恢复
公开(公告)号：US08098466B2
公开(公告)日：2012-01-17
申请号：US13066907
申请日：2011-04-26
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H02H9/00
CPC分类号： H01L27/0262 , H01L29/87
摘要： This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.
摘要翻译：本发明公开了一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在双极结型晶体管（BJT）的发射极和集电极之间的触发齐纳二极管，其中齐纳二极管的反向击穿电压BV小于或等于BJT的BVceo，其中BVceo代表集电极到发射极击穿电压，基极左开。 TVS电路还包括与BJT并联连接的整流器，用于触发整流器的整流电流，用于进一步限制反向阻断电压的增加。在优选实施例中，触发齐纳二极管，BJT和整流器通过在N阱和P阱中注入和配置第一和第二导电类型的掺杂区而形成在半导体衬底中，由此TVS可以作为电子设备的制造过程的一部分并行形成。

9. 发明申请

US20110089492A1 High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same 有权
标题翻译：具有包含介电隔离结的JFET区域的高电压半导体器件及其制造方法
公开(公告)号：US20110089492A1
公开(公告)日：2011-04-21
申请号：US12928682
申请日：2010-12-16
申请人： Hamza Yilmaz
发明人： Hamza Yilmaz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7393 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.
摘要翻译：高电压场效应器件包含延伸的漏极或“漂移”区域，包括由漂移区的中间层隔开的JFET区域的嵌入堆叠。每个JFET区域都填充有与漂移区域相反的导电类型的材料，并且每个JFET区域的地板和天花板都衬有氧化物层。当器件在断开状态下阻塞电压时，JFET区域内部和分离JFET区域的漂移区域内的半导体材料耗尽。这提高了器件的压阻能力，同时节省了芯片面积。氧化物层防止来自JFET区域的掺杂剂扩散到漂移区域。

10. 发明授权

US07906375B2 Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates 有权
标题翻译：具有高度自适应互连板的紧凑型共封装半导体管芯
公开(公告)号：US07906375B2
公开(公告)日：2011-03-15
申请号：US12832913
申请日：2010-07-08
申请人： Kai Liu , Ming Sun
发明人： Kai Liu , Ming Sun
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/495 , H01L29/00
CPC分类号： H01L24/49 , H01L23/49524 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/072 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/4103 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73221 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/37099
摘要： A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas. Consequently, the semiconductor package reduces the inter-die distance from an otherwise direct transverse circuit routing between the longitudinal edges of the dies.
摘要翻译：公开了一种半导体封装，用于在电路基板顶部封装两个相邻的半导体管芯。模具沿其纵向边缘彼此分开，具有模间距离。高度自适应电连接将模具2的顶部金属化接触件连接到模具的底表面，同时容纳表面之间的高度差。升降自适应电连接包括：a）L形电路，其是电路基板的一部分，从模具的一个纵向边缘横向延伸，并将中间接触区域放置在模具两个横向边缘旁边。 b）互连板，其在形成时将模具2的顶部金属化接触区域与中间接触区域连接，以适应接触区域之间的高度差。因此，半导体封装减少了在芯片的纵向边缘之间的另外直接的横向电路布线的晶片间距离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式