专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160148921A1 CIRCUIT CONFIGURATION AND MANUFACTURING PROCESSES FOR VERTICAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) AND EMI FILTER 审中-公开
标题翻译：用于垂直瞬态电压抑制器（TVS）和EMI滤波器的电路配置和制造工艺
公开(公告)号：US20160148921A1
公开(公告)日：2016-05-26
申请号：US14554010
申请日：2014-11-25
申请人： Shekar Mallikararjunaswamy , Madhur Bobde
发明人： Shekar Mallikararjunaswamy , Madhur Bobde
IPC分类号： H01L27/02 , H01L29/40 , H01L23/522 , H01L23/552 , H01L29/06
CPC分类号： H01L29/407 , H01L23/5223 , H01L23/552 , H01L27/0259 , H01L27/0266 , H01L29/0649 , H01L29/402 , H01L29/861 , H01L29/8611 , H01L29/8613 , H01L2924/0002 , H01L2924/00
摘要： A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
摘要翻译：垂直TVS（VTVS）电路包括用于在其上支撑VTVS器件的半导体衬底，其具有延伸到衬底底部的重掺杂层。提供深沟槽用于多声道VTVS之间的隔离。还提供沟槽门，以增加集成EMI滤波器的VTVS电容。

2. 发明申请

US20100035397A1 Configuration and method of manufacturing the one-time programmable (OTP) memory cells 有权
标题翻译：制造一次性可编程（OTP）存储单元的配置和方法
公开(公告)号：US20100035397A1
公开(公告)日：2010-02-11
申请号：US12587609
申请日：2009-10-09
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： This invention discloses a method for manufacturing a one-time programmable (OTP) memory includes a first and second MOS transistors connected in parallel and controlled by a common gate formed with a single polysilicon stripe. The method further comprises a step of implanting a drift region in a substrate region below a drain and source of the first and second MOS transistors counter doping a lightly dope drain (LDD) encompassing and surrounding a drain and a source of the first MOS transistor having a different threshold voltage than the second MOS transistor not reached by the drift region.
摘要翻译：本发明公开了一种用于制造一次可编程（OTP）存储器的方法，包括并联连接并由形成有单个多晶硅条纹的公共栅极控制的第一和第二MOS晶体管。该方法还包括在第一和第二MOS晶体管的漏极和源极下方的衬底区域中注入漂移区域的步骤，该衬底区域对掺杂包围并围绕第一MOS晶体管的漏极和源极的轻掺杂漏极（LDD）进行掺杂，与漂移区域未到达的第二MOS晶体管不同的阈值电压。

3. 发明申请

US20090262476A1 Circuit configurations to reduce snapback of a transient voltage suppressor 有权
公开(公告)号：US20090262476A1
公开(公告)日：2009-10-22
申请号：US12454333
申请日：2009-05-15
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： H02H9/00
CPC分类号： H01L27/0262 , H01L29/87
摘要： This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.

4. 发明授权

US09147674B2 Closed cell configuration to increase channel density for sub-micron planar semiconductor power device 有权
标题翻译：闭孔配置，以增加亚微米平面半导体功率器件的通道密度
公开(公告)号：US09147674B2
公开(公告)日：2015-09-29
申请号：US13134407
申请日：2011-06-06
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： H01L27/02 , H01L29/423 , H01L23/528 , H01L23/535 , H01L23/52 , H01L27/088
CPC分类号： H01L29/41758 , H01L23/52 , H01L23/528 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L29/0696 , H01L29/4238 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
摘要翻译：一种半导体功率器件，其支撑在包括多个晶体管单元的半导体衬底上，每个单元具有设置在半导体衬底中的栅极区域的相对侧上的源极和漏极区域。在栅极区域的顶部形成栅电极作为电极层，用于控制在源区和漏区之间传输的电流。设置在半导体衬底顶部的栅极电极层被图案化成波状条纹，用于基本上增加跨越栅极的源极和漏极区域之间的电流传导区域。

5. 发明授权

US08120887B2 MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage 有权
标题翻译： MOS晶体管触发瞬态电压抑制器以在较低电压下提供电路保护
公开(公告)号：US08120887B2
公开(公告)日：2012-02-21
申请号：US11712317
申请日：2007-02-28
申请人： Shekar Mallikararjunaswamy , Madhur Bobde
发明人： Shekar Mallikararjunaswamy , Madhur Bobde
IPC分类号： H02H3/22 , H02H9/00
CPC分类号： H01L27/0262 , Y10T29/49002
摘要： An electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering MOS transistor connected between an emitter and a collector of a first bipolar-junction transistor (BJT) coupled to a second BJT to form a SCR functioning as a main clamp circuit of the TVS circuit. The TVS circuit further includes a triggering circuit for generating a triggering signal for the triggering MOS transistor wherein the triggering circuit includes multiple stacked MOS transistors for turning into a conductive state by a transient voltage while maintaining a low leakage current.
摘要翻译：一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在与第二BJT耦合的第一双极结晶体管（BJT）的发射极和集电极之间的触发MOS晶体管，以形成用作TVS电路的主钳位电路的SCR。 TVS电路还包括用于产生用于触发MOS晶体管的触发信号的触发电路，其中触发电路包括多个堆叠的MOS晶体管，用于在保持低泄漏电流的同时通过瞬态电压转为导通状态。

6. 发明授权

US07602029B2 Configuration and method of manufacturing the one-time programmable (OTP) memory cells 有权
标题翻译：制造一次性可编程（OTP）存储单元的配置和方法
公开(公告)号：US07602029B2
公开(公告)日：2009-10-13
申请号：US11518001
申请日：2006-09-07
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： H01L29/72
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： This invention discloses an one time programmable (OTP) memory. The OTP memory includes a first and a second metal oxide semiconductor (MOS) transistors connected in parallel and controlled by a single polysilicon stripe functioning as a gate wherein the OTP memory further includes a drift region for counter doping a lightly dope drain (LDD) encompassing and surrounding a drain and a source of the first MOS transistor having a different threshold voltage than the second MOS transistor not reached by the drift region. In a preferred embodiment, the first and second MOS transistors are N-MOS transistors disposed in a common P-well and the drift region of the first MOS transistor further comprising a P-drift region.
摘要翻译：本发明公开了一种可编程（OTP）存储器。 OTP存储器包括并联连接并由用作栅极的单个多晶硅条纹控制的第一和第二金属氧化物半导体（MOS）晶体管，其中OTP存储器还包括漂移区域，用于反向掺杂包含着色层的轻掺杂漏极（LDD）并且围绕具有与漂移区域未到达的第二MOS晶体管不同的阈值电压的第一MOS晶体管的漏极和源极。在优选实施例中，第一和第二MOS晶体管是N沟道MOS晶体管，其设置在公共P阱中，并且第一MOS晶体管的漂移区域还包括P漂移区域。

7. 发明申请

US20070295996A1 Closed cell configuration to increase channel density for sub-micron planar semiconductor power device 有权
标题翻译：闭孔配置，以增加亚微米平面半导体功率器件的通道密度
公开(公告)号：US20070295996A1
公开(公告)日：2007-12-27
申请号：US11473938
申请日：2006-06-23
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： H01L27/10
CPC分类号： H01L29/41758 , H01L23/52 , H01L23/528 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L29/0696 , H01L29/4238 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
摘要翻译：一种半导体功率器件，其支撑在包括多个晶体管单元的半导体衬底上，每个单元具有设置在半导体衬底中的栅极区域的相对侧上的源极和漏极区域。在栅极区域的顶部形成栅电极作为电极层，用于控制在源区和漏区之间传输的电流。设置在半导体衬底顶部的栅极电极层被图案化成波状条纹，用于基本上增加跨越栅极的源极和漏极区域之间的电流传导区域。

8. 发明授权

US08896093B2 Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter 有权
标题翻译：垂直瞬态电压抑制器（TVS）和EMI滤波器的电路配置和制造工艺
公开(公告)号：US08896093B2
公开(公告)日：2014-11-25
申请号：US13720042
申请日：2012-12-19
申请人： Shekar Mallikararjunaswamy , Madhur Bobde
发明人： Shekar Mallikararjunaswamy , Madhur Bobde
IPC分类号： H01L29/73 , H01L27/02 , H01L21/02 , H01L29/861 , H01L23/60 , H01L29/732 , H01L27/07
CPC分类号： H01L27/0248 , H01L21/02365 , H01L23/60 , H01L27/0255 , H01L27/0727 , H01L29/0649 , H01L29/407 , H01L29/7304 , H01L29/7322 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
摘要翻译：垂直TVS（VTVS）电路包括用于在其上支撑VTVS器件的半导体衬底，其具有延伸到衬底底部的重掺杂层。提供深沟槽用于多声道VTVS之间的隔离。还提供沟槽门，以增加集成EMI滤波器的VTVS电容。

9. 发明申请

US20110237038A1 Closed cell configuration to increase channel density for sub-micron planar semiconductor power device 审中-公开
标题翻译：闭孔配置，以增加亚微米平面半导体功率器件的通道密度
公开(公告)号：US20110237038A1
公开(公告)日：2011-09-29
申请号：US13134407
申请日：2011-06-06
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： H01L21/336
CPC分类号： H01L29/41758 , H01L23/52 , H01L23/528 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L29/0696 , H01L29/4238 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
摘要翻译：一种半导体功率器件，其支撑在包括多个晶体管单元的半导体衬底上，每个单元具有设置在半导体衬底中的栅极区域的相对侧上的源极和漏极区域。在栅极区域的顶部形成栅电极作为电极层，用于控制在源区和漏区之间传输的电流。设置在半导体衬底顶部的栅极电极层被图案化成波状条纹，用于基本上增加跨越栅极的源极和漏极区域之间的电流传导区域。

10. 发明授权

US07489535B2 Circuit configurations and methods for manufacturing five-volt one time programmable (OTP) memory arrays 有权
标题翻译：用于制造五伏一次可编程（OTP）存储器阵列的电路配置和方法
公开(公告)号：US07489535B2
公开(公告)日：2009-02-10
申请号：US11588736
申请日：2006-10-28
申请人： Shekar Mallikararjunaswamy
发明人： Shekar Mallikararjunaswamy
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L27/0207 , H01L27/112 , H01L27/11206
摘要： This invention discloses a circuit trimming system that includes a one-time programmable memory (OTP). The OTP further includes a forward biased trim device connected between a voltage supply Vcc and a ground voltage wherein the Vcc having a reduced voltage substantially lower than a trimming voltage for a reversed biased device at ten volts or higher. The OTP further includes a drive circuit provided to select the OTP at a low current operating condition and for turning on a high trim current through the forward biased trim device for trimming and programming the OTP. The trimming system further includes a sense circuit connected across the forward biased trim device is for sensing a current and voltage of the forward biased trim device.
摘要翻译：本发明公开了一种包括一次可编程存储器（OTP）的电路修整系统。 OTP还包括连接在电压源Vcc和接地电压之间的正向偏置调整装置，其中Vcc的电压基本上低于用于十伏或更高的反向偏置装置的微调电压。 OTP还包括提供用于在低电流操作条件下选择OTP的驱动电路，以及通过正向偏置调整装置接通高调整电流以修整和编程OTP。修整系统还包括连接在正向偏置的装饰装置上的感测电路，用于感测正向偏置的装饰装置的电流和电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式