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81. 发明授权

US6163174A Digital buffer circuits 失效
标题翻译：数字缓冲电路
公开(公告)号：US6163174A
公开(公告)日：2000-12-19
申请号：US318421
申请日：1999-05-25
申请人： Eby Friedman , Radu M. Secareanu
发明人： Eby Friedman , Radu M. Secareanu
IPC分类号： G11C5/06 , G11C7/10 , H03K19/00 , H03K19/017 , G11C8/00
CPC分类号： H03K19/01707 , G11C5/063 , G11C7/1051 , G11C7/1078 , H03K19/0013
摘要： CMOS buffer circuits are provided having multiple stages of driving transistors defining a fast "1" data path and a fast "0" data path for transmitting data signals from the input to output of the buffer. Each stage before the last stage in each of the data paths has at least one nulling transistor coupled to the driving transistor of the stage. Separate from the data paths, the nulling transistors of each data path are operated to synchronously null the driving transistors of the data path to prepare such driving transistors for the next fast transition in the input data signal. Another nulling transistor may be also coupled to the driving transistor of each stage before the last stage of each data path which prevents the data path from floating when the data path is not transmitting a transition of the input signal to output of the buffer. The CMOS buffer circuits are suitable for driving large capacitive loads optimally over any range of input signal frequency, restoring slow transitioning digital signals, or driving highly resistive RC interconnect lines.
摘要翻译：提供CMOS缓冲电路，其具有定义快速“1”数据通道的多级驱动晶体管和用于从缓冲器的输入到输出的数据信号传输的快速“0”数据通路。在每个数据路径中的最后阶段之前的每一级具有耦合到该级的驱动晶体管的至少一个零位晶体管。与数据路径分开，操作每个数据通路的零位晶体管以使数据通路的驱动晶体管同步失真，以准备用于输入数据信号中的下一个快速转换的驱动晶体管。另外的零陷晶体管也可以在每个数据路径的最后阶段之前的每一级的驱动晶体管耦合，当数据路径不传输输入信号到缓冲器的输出时，防止数据路径浮动。 CMOS缓冲电路适用于在任何范围的输入信号频率，恢复慢速转换数字信号或驱动高电阻RC互连线路上最佳地驱动大容性负载。

82. 发明授权

US6157216A Circuit driver on SOI for merged logic and memory circuits 有权
标题翻译： SOI上的电路驱动器用于合并逻辑和存储器电路
公开(公告)号：US6157216A
公开(公告)日：2000-12-05
申请号：US296875
申请日：1999-04-22
申请人： George McNeil Lattimore , Donald George Mikan, Jr. , Binta Minesh Patel , Gus Wai-Yan Yeung
发明人： George McNeil Lattimore , Donald George Mikan, Jr. , Binta Minesh Patel , Gus Wai-Yan Yeung
IPC分类号： G11C11/418 , G11C11/407 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/786 , H03K19/003 , H03K19/017 , H03K19/0175
CPC分类号： H03K19/01707
摘要： A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.
摘要翻译：一种具有体电压控制级和电压钳位级的绝缘体上硅数字电路组合。体电压控制级响应于输入控制信号以提供输出驱动器信号。体电压控制级具有第一晶体管，其具有用于电耦合到组合逻辑电路的端子和与输入控制信号电耦合的体接触，使得当晶体管放置在晶体管时晶体管的阈值电压降低活跃状态。可以容易地理解，晶体管的降低的阈值电压响应于输入控制信号将第一晶体管的转变速率增加到无效状态。电压钳位级具有响应于输入控制信号的第二晶体管，使得当第一晶体管处于非活动状态时，端子与参考电压电耦合。

83. 发明授权

US6154397A Semiconductor memory device having stabilization circuit for stable signal transmission 有权
标题翻译：具有用于稳定信号传输的稳定电路的半导体存储器件
公开(公告)号：US6154397A
公开(公告)日：2000-11-28
申请号：US471518
申请日：1999-12-23
申请人： Shin-Ho Chu , Je-Hun Ryu
发明人： Shin-Ho Chu , Je-Hun Ryu
IPC分类号： G11C11/41 , G11C7/10 , G11C11/409 , H03K19/017 , G11C7/00
CPC分类号： G11C7/1048
摘要： A semiconductor memory device includes a transmission line, connected to a driving unit, for transmitting a signal from the driving unit, a delaying unit for delaying a level of the transmission line to output the delayed signal, a precharging unit for receiving the delayed signal to precharge the transmission line, and a stabilization unit for accelerating the level transition of the transmission line, wherein the stabilization unit includes a detecting unit for detecting the level of the transmission line transmitted from the driving unit to generate a detected signal, and a switching unit for performing a switching operation in response to the detected level to swiftly achieve a level transition of the transmission line.
摘要翻译：一种半导体存储器件，包括：连接到驱动单元的传输线，用于从驱动单元发送信号;延迟单元，用于延迟传输线的电平以输出延迟信号;预充电单元，用于接收延迟信号以及用于加速传输线路的电平转换的稳定单元，其中稳定单元包括用于检测从驱动单元发送的传输线的电平以产生检测信号的检测单元，以及切换单元用于响应于检测到的电平执行切换操作，以迅速实现传输线的电平转换。

84. 发明授权

US6137316A Integrated circuit with improved off chip drivers 失效
公开(公告)号：US6137316A
公开(公告)日：2000-10-24
申请号：US93797
申请日：1998-06-09
申请人： Steffen Loeffler , Peter Poechmueller
发明人： Steffen Loeffler , Peter Poechmueller
IPC分类号： G11C11/407 , G06F1/10 , G11C11/40 , G11C11/401 , H01L21/822 , H01L27/04 , H03K17/04 , H03K17/687 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0185
CPC分类号： G06F1/10 , H03K19/00323 , H03K19/01721
摘要： An array of multiple off chip drivers on an integrated circuit (IC) chip has reduced synchronous switching output timing error (TSSO) at high speeds of operation. The array includes a pair of low resistance buses to provide charge and discharge paths for the outputs, a plurality of terminals connecting the respective drivers between the buses, the resistance of each terminal being substantially greater than the resistance of either bus, and a plurality of capacitors connected internally of the respective drivers. Each driver has an input for receiving binary data from a memory unit and an output terminal which is switched in accordance with the binary input data to a higher or lower voltage level. There are a plurality of transistor switches within each driver which selectively couple a capacitor to the output terminal when it is driven high and at the same time couple another capacitor to one of the buses, and vice versa when the output terminal is driven low.

85. 发明授权

US6066963A MOS output driver, and circuit and method of controlling same 失效
公开(公告)号：US6066963A
公开(公告)日：2000-05-23
申请号：US939196
申请日：1997-09-29
申请人： William G. Baker
发明人： William G. Baker
IPC分类号： H03K19/017 , H03K19/0175
CPC分类号： H03K19/01721
摘要： A circuit and method for providing a fast transitioning output buffer that may be configured to operate using either a 3 volt or 5 volt supply voltage. The pullup behaves similarly to a MOS diode, but the circuit lowers the gate voltage on a pullup while the output is being pulled up. The circuit does not affect the final pullup voltage. As a result, a single PMOS device may be used as a pullup device that does not generally require an increased size to support a high operating voltage.

86. 发明授权

US6049504A Pulse driver 有权
标题翻译：脉冲驱动器
公开(公告)号：US6049504A
公开(公告)日：2000-04-11
申请号：US211139
申请日：1998-12-16
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C11/40 , G11C7/22 , H03K5/00 , H03K5/13 , H03K19/017 , G11C8/00
CPC分类号： H03K19/01721 , G11C7/22 , H03K5/133 , H03K2005/00078
摘要： An inventive pulse driver transmits a pulse signal in a high speed when the pulse signal is coupled thereto. For the purpose, the pulse driver comprises a first and a second CMOS inverters connected in series, a first inverting delay unit for delaying and phase-shifting an input signal coupled to the first CMOS inverter, a first regulating device, connected to an output terminal of the first CMOS inverter, for adjusting the output signal of the first CMOS inverter in response to an output signal of the first inverting delay unit, a second inverting delay unit for delaying and phase-shifting a signal which is outputted from the first CMOS inverter and inputted to the second CMOS inverter and a second regulating device, connected to the output terminal of the second CMOS inverter, for adjusting the output signal of the second CMOS inverter responsive to an output signal of the second inverting delay unit. Therefore, the pulse driver can drive a pulse signal in a high speed as twice as a conventional pulse driver. In addition, when the pulse driver is adopted to a clock driver, it can be advantageously applied to a delay lock loop (DLL) circuit since there is less change of delay.
摘要翻译：当脉冲信号耦合到其上时，本发明的脉冲驱动器以高速度传送脉冲信号。为此，脉冲驱动器包括串联连接的第一和第二CMOS反相器，用于延迟和相移耦合到第一CMOS反相器的输入信号的第一反相延迟单元，连接到输出端子的第一调节装置的第一CMOS反相器，用于响应于第一反相延迟单元的输出信号调整第一CMOS反相器的输出信号;第二反相延迟单元，用于延迟和相移从第一CMOS反相器输出的信号并输入到第二CMOS反相器和连接到第二CMOS反相器的输出端的第二调节装置，用于响应于第二反相延迟单元的输出信号调整第二CMOS反相器的输出信号。因此，脉冲驱动器可以高速驱动脉冲信号，是常规脉冲驱动器的两倍。此外，当将脉冲驱动器应用于时钟驱动器时，由于延迟的变化较小，所以可以有利地应用于延迟锁定环路（DLL）电路。

87. 发明授权

US6040715A Output buffer control circuit that performs high speed operation by generating a predetermined width of a pulse based on an output control signal 失效
标题翻译：输出缓冲器控制电路，其通过基于输出控制信号产生脉冲的预定宽度来执行高速操作
公开(公告)号：US6040715A
公开(公告)日：2000-03-21
申请号：US893613
申请日：1997-07-11
申请人： Hee-Bok Kang , Dae-Hui Kim
发明人： Hee-Bok Kang , Dae-Hui Kim
IPC分类号： G11C11/41 , G11C11/417 , H03K19/00 , H03K19/017 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/01742
摘要： An output buffer control circuit is provided in which a three-phase (state) level of an output warning can be realized in a short time, which results in increasing the processing speed. The output buffer control circuit uses a predetermined width pulse at the point when the output control signal is changed to low level. The predetermined width pulse is operated with the previous output signal and the resultant signal feeds back to the output terminal. The output buffer control circuit includes a first data latch unit for inverting and latching input data when a latch signal is high level, a data output unit for logically operating an output signal from the first data latch unit based on an output control signal and generating an output data, a second data latch unit for inverting and latching the output signal from the first data latch unit when the output control signal is high level, a signal detector for generating a predetermined width pulse at the point when the output control signal is shifted to low level, and an output terminal pre-reset unit for logically operating the pulse outputted from the signal detector and the output signal from the second data latch unit to pre-reset the output terminal of the data output unit.
摘要翻译：提供一种输出缓冲器控制电路，其中可以在短时间内实现输出警告的三相（状态）电平，这导致处理速度的提高。输出缓冲器控制电路在输出控制信号变为低电平时使用预定的宽度脉冲。预定的宽度脉冲用先前的输出信号进行操作，并且所得到的信号反馈到输出端。输出缓冲器控制电路包括：第一数据锁存单元，用于当锁存信号为高电平时反相和锁存输入数据;数据输出单元，用于基于输出控制信号逻辑地操作来自第一数据锁存单元的输出信号，输出数据，第二数据锁存单元，用于在输出控制信号为高电平时反相并锁存来自第一数据锁存单元的输出信号;信号检测器，用于在输出控制信号转换到以及输出端子预复位单元，用于逻辑地操作从信号检测器输出的脉冲和来自第二数据锁存单元的输出信号，以预复位数据输出单元的输出端。

88. 发明授权

US6023179A Method of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flop 失效
标题翻译：使用边沿触发静态动态触发器实现扫描触发器的方法
公开(公告)号：US6023179A
公开(公告)日：2000-02-08
申请号：US868981
申请日：1997-06-04
申请人： Edgardo F. Klass
发明人： Edgardo F. Klass
IPC分类号： H03K3/037 , H03K19/017
CPC分类号： H03K3/0372
摘要： A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the precharge phase in which a dynamic input stage is precharged and a static output stage maintains the output signal from the previous evaluation phase. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.
摘要翻译：实现用于逻辑门的扫描片的方法包括将触发器配置成扫描模式或数据模式。然后触发器进入预充电阶段，其中动态输入级被预充电，静态输出级保持来自先前评估阶段的输出信号。在正常模式的评估阶段期间，动态输入级产生一个输出信号，该输出信号保持在逻辑高电平，或者从高到低转换，补充数据信号的逻辑电平。在扫描模式的评估阶段期间，动态输入级产生保持在逻辑高电平的输出信号，或者从高到低转换，补充扫描输入信号的逻辑电平。静态输出级接收来自动态输入级的输出信号和时钟信号。在评估阶段，静态输出级输出从动态输入级接收的输出信号的补码。

89. 发明授权

US5969542A High speed gate oxide protected level shifter 失效
标题翻译：高速栅极氧化物保护电平转换器
公开(公告)号：US5969542A
公开(公告)日：1999-10-19
申请号：US861038
申请日：1997-05-21
申请人： Reading Maley , Albrecht Schoy
发明人： Reading Maley , Albrecht Schoy
IPC分类号： H03K3/012 , H03K3/356 , H03K17/10 , H03K19/0185 , H03K19/017
CPC分类号： H03K3/012 , H03K17/102 , H03K3/356147
摘要： An improved gate oxide protected level shifter is provided which has a higher speed of operation than is traditionally available. The level shifter includes a first capacitor coupled between a first output terminal and the input of an inverter and a second capacitor coupled between a first node and the output of the inverter. As a result, the speed of the transitions at the gates of the pair of cross-coupled P-channel MOS transistors is increased several times.
摘要翻译：提供了一种改进的栅氧化物保护电平转换器，其具有比传统可用的更高的操作速度。电平移位器包括耦合在第一输出端子和反相器的输入端之间的第一电容器和耦合在第一节点和反相器的输出端之间的第二电容器。结果，在一对交叉耦合的P沟道MOS晶体管的栅极处的转变速度增加了几倍。

90. 发明授权

US5966044A Pull-up circuit and semiconductor device using the same 失效
标题翻译：上拉电路和使用其的半导体器件
公开(公告)号：US5966044A
公开(公告)日：1999-10-12
申请号：US964461
申请日：1997-11-04
申请人： Naoaki Naka
发明人： Naoaki Naka
IPC分类号： G06F3/00 , H03K19/003 , H03K19/017 , H03K19/0175 , G05F1/10 , G05F3/02
CPC分类号： H03K19/01721 , H03K19/00315
摘要： A pull-up circuit includes a pull-up transistor of a P-channel type having a drain coupled to a bus via a terminal, a source, a gate and a back gate, and a control circuit controlling the pull-up transistor so that no currents flow in a first current path formed from the drain to the back gate and a second path formed from the drain to the source.
摘要翻译：上拉电路包括一个P沟道型的上拉晶体管，其具有通过端子耦合到总线的漏极，源极，栅极和背栅极，以及控制上拉晶体管的控制电路，使得在从漏极到后栅极形成的第一电流路径中没有电流流动，以及从漏极到源极形成的第二路径。

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