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1. 发明授权

US06269029B1 Semi-conductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06269029B1
公开(公告)日：2001-07-31
申请号：US09607194
申请日：2000-06-28
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1006
摘要： The present invention relates to a semi-conductor memory device, comprises global data bus lines and single data strobe lines and reference comparing voltage lines with the number being identical to the number of data being coupled between a bank and an input, output interface circuit part; a clamping means connected every each line for fixing the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines to a regular level of an electric potential; a first to a third driving means connected to every ends of both sides of the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines, for controlling a drive of each lines by a combination of an input, output enable signal and a data output strobe signal and each data signal; a first receiving means connected to ends of both sides of the data strobe lines, for receiving a strobe signal carried on the data strobe lines and comparing it with a reference comparing voltage and thereby outputting the data strobe signal; a second receiving means connected to respective ends of both sides of the numerous global data bus lines, for comparing each data signal with a reference comparing voltage signal and outputting each data value under a control of a data strobe signal being outputted from the first receiving means.
摘要翻译：半导体存储器件技术领域本发明涉及一种半导体存储器件，包括全局数据总线和单数据选通线以及参考比较电压线，其数量与耦合在存储体和输入端之间的数据数量相同，输出接口电路部分 ; 每个线路连接的夹持装置，用于将许多全局数据总线和数据选通线和参考比较电压线固定成规定的电位电平; 连接到多个全局数据总线两端的每一端的第一至第三驱动装置以及数据选通线和参考比较电压线，用于通过输入，输出使能信号的组合来控制每行的驱动和数据输出选通信号和每个数据信号; 连接到所述数据选通线的两端的端部的第一接收装置，用于接收数据选通线上承载的选通信号，并将其与参考比较电压进行比较，从而输出所述数据选通信号; 连接到多个全局数据总线的两侧的各端的第二接收装置，用于将每个数据信号与参考比较电压信号进行比较，并在从第一接收装置输出的数据选通信号的控制下输出每个数据值。

2. 发明授权

US6160754A Synchronous memory device of a wave pipeline structure 有权
标题翻译：波形管道结构的同步存储器件
公开(公告)号：US6160754A
公开(公告)日：2000-12-12
申请号：US320216
申请日：1999-05-26
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/413 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1072
摘要： A synchronous memory device of a wave pipeline structure includes: an internal clock signal generation means which generates an internal clock signal being a standard of an output data only during a period in which an output enable signal is activated; and a data transmission means which is connected between an output terminal of a plurality of registers and an output driver, is switched by a control of the internal clock signal, receives data stored in an activated register as input, and transmits the data to the output driver. As a result, the synchronous memory device greatly improves the data access path and the data output hold time, enhances the stability and performance of a memory operation, and achieves a high-speed operation.
摘要翻译：波形管线结构的同步存储器件包括：内部时钟信号产生装置，其仅在输出使能信号被激活的时段内产生作为输出数据标准的内部时钟信号; 并且连接在多个寄存器的输出端和输出驱动器之间的数据传输装置通过内部时钟信号的控制进行切换，接收存储在激活的寄存器中的数据作为输入，并将数据发送到输出司机。结果，同步存储装置极大的提高了数据存取路径和数据输出保持时间，提高了存储器运行的稳定性和性能，实现了高速运行。

3. 发明授权

US06226207B1 Semiconductor device having an electric charge amplifier for amplifying bit line electric charge 失效
标题翻译：具有用于放大位线电荷的电荷放大器的半导体器件
公开(公告)号：US06226207B1
公开(公告)日：2001-05-01
申请号：US09099766
申请日：1998-06-19
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C11/4091
摘要： In a dynamic random access memory (DRAM) being operated at a low power-supply voltage, a bit line sense-amplifier for amplifying the electric charge first amplifies a cell charge applied to a bit line with a sufficient potential difference, prior to sensing the cell charge in a bit line sense-amplifier, thereby stably and quickly performing a sensing operation. In a semiconductor memory device having a cell array block having a plurality of memory cells, and a bit line sense-amplifier for sensing and amplifying a cell charge transmitted to a true bit line or a complement bit line, a bit line sense-amplifier for amplifying the electric charge includes: an electric charge amplifier which amplifies the cell charge transmitted to the true bit line and the complement bit line with a sufficient potential difference, and then transmits the amplified cell charge to the bit line sense-amplifier; and a switching element which is connected to the true bit line and the complement bit line between the cell array block and the electric charge amplifier, and switches a connection between the cell array block and the electric charge amplifier.
摘要翻译：在以低电源电压工作的动态随机存取存储器（DRAM）中，用于放大电荷的位线读出放大器首先在感测到电荷之前放大施加到位线的电池电荷，在位线读出放大器中的电池充电，从而稳定且快速地进行感测操作。在具有具有多个存储单元的单元阵列块的半导体存储器件和用于感测和放大传输到真位线或补码位线的单元电荷的位线读出放大器中，位线读出放大器用于放大电荷包括：电荷放大器，其以足够的电位差放大传输到真位线和补码位线的单元电荷，然后将放大的单元电荷发送到位线读出放大器; 以及连接到单元阵列块和电荷放大器之间的真位线和补码位线的开关元件，并且切换单元阵列块和电荷放大器之间的连接。

4. 发明授权

US06209056B1 Semiconductor memory device having a plurality of bank sections distributed in a plurality of divided memory cell arrays 失效
标题翻译：半导体存储器件具有分布在多个划分的存储单元阵列中的多个堤区
公开(公告)号：US06209056B1
公开(公告)日：2001-03-27
申请号：US08885035
申请日：1997-06-30
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G06F1206
CPC分类号： G11C5/025 , G11C5/063 , G11C7/10
摘要： A semiconductor memory device has a plurality of memory cell arrays with a plurality of bank sections. Bank sections identified by different sequence numbers are operated independently of each other. A plurality of data bus lines transfer data in order to write into a desired bank section in each of the memory cell arrays and to read data from the desired bank section in each of the memory cell arrays. The desired bank sections with a same sequence number in each of memory cell arrays are selected simultaneously by a vertical and horizontal bank selection signal.
摘要翻译：半导体存储器件具有多个存储单元阵列和多个存储单元阵列。由不同序列号标识的银行部分彼此独立地操作。多个数据总线线路传输数据以便写入每个存储单元阵列中的期望的存储体部分，并从每个存储单元阵列中的期望存储体部分读取数据。通过垂直和水平存储体选择信号同时选择在每个存储单元阵列中具有相同序列号的期望存储区段。

5. 发明授权

US6049504A Pulse driver 有权
标题翻译：脉冲驱动器
公开(公告)号：US6049504A
公开(公告)日：2000-04-11
申请号：US211139
申请日：1998-12-16
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C11/40 , G11C7/22 , H03K5/00 , H03K5/13 , H03K19/017 , G11C8/00
CPC分类号： H03K19/01721 , G11C7/22 , H03K5/133 , H03K2005/00078
摘要： An inventive pulse driver transmits a pulse signal in a high speed when the pulse signal is coupled thereto. For the purpose, the pulse driver comprises a first and a second CMOS inverters connected in series, a first inverting delay unit for delaying and phase-shifting an input signal coupled to the first CMOS inverter, a first regulating device, connected to an output terminal of the first CMOS inverter, for adjusting the output signal of the first CMOS inverter in response to an output signal of the first inverting delay unit, a second inverting delay unit for delaying and phase-shifting a signal which is outputted from the first CMOS inverter and inputted to the second CMOS inverter and a second regulating device, connected to the output terminal of the second CMOS inverter, for adjusting the output signal of the second CMOS inverter responsive to an output signal of the second inverting delay unit. Therefore, the pulse driver can drive a pulse signal in a high speed as twice as a conventional pulse driver. In addition, when the pulse driver is adopted to a clock driver, it can be advantageously applied to a delay lock loop (DLL) circuit since there is less change of delay.
摘要翻译：当脉冲信号耦合到其上时，本发明的脉冲驱动器以高速度传送脉冲信号。为此，脉冲驱动器包括串联连接的第一和第二CMOS反相器，用于延迟和相移耦合到第一CMOS反相器的输入信号的第一反相延迟单元，连接到输出端子的第一调节装置的第一CMOS反相器，用于响应于第一反相延迟单元的输出信号调整第一CMOS反相器的输出信号;第二反相延迟单元，用于延迟和相移从第一CMOS反相器输出的信号并输入到第二CMOS反相器和连接到第二CMOS反相器的输出端的第二调节装置，用于响应于第二反相延迟单元的输出信号调整第二CMOS反相器的输出信号。因此，脉冲驱动器可以高速驱动脉冲信号，是常规脉冲驱动器的两倍。此外，当将脉冲驱动器应用于时钟驱动器时，由于延迟的变化较小，所以可以有利地应用于延迟锁定环路（DLL）电路。

6. 发明授权

US5781498A Sub word line driving circuit and a semiconductor memory device using the same 失效
公开(公告)号：US5781498A
公开(公告)日：1998-07-14
申请号：US764083
申请日：1996-12-06
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C11/41 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/408 , G11C11/418 , G11C8/00
CPC分类号： G11C8/14 , G11C11/4085 , G11C8/08
摘要： A sub word line driving circuit for driving a sub word line is used for a semiconductor memory device having a hierarchical word line structure. The sub word line driving circuit includes two NMOS transistors for driving the sub word lines to reduce an area of overall memory device when being applied to a VLSI memory device of Gigabit class while there is no time loss caused by delay between driving signals heretofore required in a bootstrap process to involve high operating speed and to be favorable in a reliability aspect of the device.

7. 发明授权

US5757692A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5757692A
公开(公告)日：1998-05-26
申请号：US727852
申请日：1996-10-04
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C11/401 , G11C11/407 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C11/24
CPC分类号： G11C11/4097 , G11C11/4091
摘要： The semiconductor memory device having a cell array of a folded bit line structure according to the present invention comprises main bit lines MB1 and MB2 and m sub-bit lines SB1i and SB2i (1.ltoreq.i.ltoreq.m), which detect amplifiers connected to both ends of the main bit lines, respectively, two sub-bit line block selection switching means for connecting the main bit line with respective sub-bit lines according to a block selection signal SBi, and a main bit line separation switching means connected between the two sub-bit line block selection switching means, for dividing the main bit line into two equal parts according to a main bit line separation signal. The number of cells connected to the bit lines is increased and the number of whole detect amplifiers is decreased, which may reduce the size of the chip so as to reduce the fabricating costs of the memory product.
摘要翻译：具有根据本发明的折叠位线结构的单元阵列的半导体存储器件包括主位线MB1和MB2以及m个子位线SB1i和SB2i（1≤i≤m），其检测放大器分别连接到主位线的两端，两个子位线块选择切换装置，用于根据块选择信号SBi将主位线与各个子位线连接，以及主位线分离切换装置在两个子位线块选择切换装置之间，用于根据主位线分离信号将主位线分成两个相等的部分。连接到位线的单元数量增加，并且整个检测放大器的数量减少，这可能减小芯片的尺寸，从而降低存储器产品的制造成本。

8. 发明授权

US6140841A High speed interface apparatus 有权
标题翻译：高速接口设备
公开(公告)号：US6140841A
公开(公告)日：2000-10-31
申请号：US342222
申请日：1999-06-29
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G06F3/00 , H01L27/04 , H03M13/00 , H04L25/02 , H04L25/49 , H03K19/00
CPC分类号： H04L25/028 , H03M13/00 , H04L25/0278 , H04L25/0292 , H04L25/4917 , H04L25/0276
摘要： The present invention discloses a much higher speed interface apparatus which comprises a data driving means for decoding two-bit data signals using them as inputs to output four-level data signals; a reference voltage generating means for generating three-level reference voltages to discriminate the voltage levels of the four-level data signals; and a receiver means for comparing the four-level data signals and the three-level reference voltage signals using them as inputs and for encoding the resulting signals to output two data signals.
摘要翻译：本发明公开了一种更高速度的接口设备，它包括一个数据驱动装置，用于使用它们作为输出来输出四电平数据信号的两位数据信号进行解码; 参考电压产生装置，用于产生三电平参考电压以鉴别四电平数据信号的电压电平; 以及用于将四电平数据信号和三电平参考电压信号作为输入进行比较并用于对所得到的信号进行编码以输出两个数据信号的接收机装置。

9. 发明授权

US6006290A System for performing high speed burst operation in memory device utilizing CAS clock to control and activate /WE and /OE control signals 失效
标题翻译：用于在利用CAS时钟来控制和激活/ WE和/ OE控制信号的存储器件中执行高速脉冲串操作的系统
公开(公告)号：US6006290A
公开(公告)日：1999-12-21
申请号：US968500
申请日：1997-11-12
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C11/401 , G06F12/02 , G11C7/00 , G11C7/10 , G06F1/04 , G06F1/12
CPC分类号： G11C7/1024
摘要： Disclosed a conrol method and an apparatus for performing high speed burst operation in memory device which can perform high speed burst read/write operations at a speed superior to be superior to an operation speed of a burst EDO mode type DRAM by shortening a CAS access time tCAC, and can produce an identical package using signals which are used in a memory device of a EDO mode type DRAM. The method comprising the steps of preparing an "Idle" status where an internal circuit is precharged after a "Power On" status, determining a read mode, a write mode, a read/write mode, or a write/read mode in accordance with a /WE signal at a falling edge of a /CAS signal in which a column address is inputted in a case of a "Row Open" status by an instruction which is inputted during the "Idle" status, and automatically returning to the "Row Open" status if an operation of the read, write, read/write, or write/read mode is ended. Accordingly, the present invention can be used for a 66 MHz bus clock frequency which can not be applied to the conventional burst EDO mode type DRAM, and for the next generation 75-100 MHz bus clocks frequency. Further, there is an advantage that the present invention does not use the external clock, unlike a synchronous type DRAM, thereby reducing the power consumption of the total memory system.
摘要翻译：公开了一种用于在存储器件中执行高速脉冲串操作的控制方法和装置，其可以通过缩短CAS访问时间来以优于突发EDO模式型DRAM的操作速度的速度执行高速突发读/写操作 tCAC，并且可以使用在EDO模式型DRAM的存储器件中使用的信号来产生相同的封装。该方法包括以下步骤：准备“空闲”状态，其中内部电路在“开机”状态之后被预先充电，根据以下方式确定读取模式，写入模式，读取/写入模式或写入/读取模式在通过在“空闲”状态期间输入的指令在“行打开”状态的情况下输入列地址的/ CAS信号的下降沿处的a / WE信号，并自动返回到“行如果读，写，读/写或写/读模式的操作结束，则打开“状态。因此，本发明可以用于不能应用于常规突发EDO模式型DRAM和下一代75-100MHz总线时钟频率的66MHz总线时钟频率。此外，与同步型DRAM不同，本发明不利用外部时钟，从而降低了总存储器系统的功耗。

10. 发明授权

US5835439A Sub word line driving circuit and a semiconductor memory device using the same 失效
标题翻译：子字线驱动电路和使用其的半导体存储器件
公开(公告)号：US5835439A
公开(公告)日：1998-11-10
申请号：US887280
申请日：1997-07-02
申请人： Jung Won Suh
发明人： Jung Won Suh
IPC分类号： G11C11/41 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/408 , G11C11/418 , G11C7/00 , G11C8/00
CPC分类号： G11C8/14 , G11C11/4085 , G11C8/08
摘要： A sub word line driving circuit for driving a sub word line is used for a semiconductor memory device having a hierarchical word line structure. The sub word line driving circuit includes two NMOS transistors for driving the sub word lines to reduce an area of overall memory device when being applied to a VLSI memory device of Gigabit class while there is no time loss caused by delay between driving signals heretofore required in a bootstrap process to involve high operating speed and to be favorable in a reliability aspect of the device.
摘要翻译：用于驱动子字线的子字线驱动电路用于具有分层字线结构的半导体存储器件。子字线驱动电路包括用于驱动子字线的两个NMOS晶体管，以便在应用于千兆级的VLSI存储器件时减小总体存储器件的面积，而不存在由于以前需要的驱动信号之间的延迟引起的时间损失引导过程涉及高操作速度并且在设备的可靠性方面是有利的。

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