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81. 发明申请

US20020140455A1 Level shift circuit for stepping up logic signal amplitude with improved operating speed 审中-公开
标题翻译：电平移位电路，提高逻辑信号幅度，提高工作速度
公开(公告)号：US20020140455A1
公开(公告)日：2002-10-03
申请号：US09988616
申请日：2001-11-20
申请人： FUJITSU LIMITED
发明人： Seiichiro Yamaguchi
IPC分类号： H03K019/0175
CPC分类号： H03K3/356113 , H03K17/102
摘要： NMOS transistors N3 and N3S are connected in series between a PMOS transistor P1 and an NMOS transistor N1S constituting a first inverter connected between a power supply potential VDD2, which satisfies VDD1
摘要翻译： NMOS晶体管N3和N3S串联连接在构成连接在满足VDD1

82. 发明申请

US20020130682A1 Adaptive threshold logic circuit 有权
公开(公告)号：US20020130682A1
公开(公告)日：2002-09-19
申请号：US09805100
申请日：2001-03-14
发明人： David J. Warner
IPC分类号： H03K019/0175
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078 , G11C7/1084 , H03K19/0005 , H03K19/0027 , H03K19/018585
摘要： An adaptive threshold logic circuit is provided in which the switching threshold levels of the logic circuit are automatically changed to accommodate variations in the level of applied data signals to the switching circuit. A detector stage detects the voltage level of the incoming data signals and selectively adjusts the threshold level of a threshold adaptor stage in accordance with the output of the detector stage. The threshold adaptor stage is essentially an adaptive CMOS inverter having various switching paths turned on or off in accordance with the output of the detector stage.

83. 发明申请

US20020097068A1 System and method for improving signal propagation 有权
标题翻译：改善信号传播的系统和方法
公开(公告)号：US20020097068A1
公开(公告)日：2002-07-25
申请号：US09766756
申请日：2001-01-22
申请人： Micron Technology, Inc.
发明人： Donald M. Morgan
IPC分类号： H03K019/0175
CPC分类号： H04L25/242 , H03K19/01707
摘要： Systems and methods are provided for improving signal propagation. A repeater segments a transmission line into a first and a second line. The repeater includes an inverting amplifier and an equilibration circuit. The inverting amplifier has an input connected to the first line and an output connected to the second line. The amplifier receives and an input signal at a first logic potential and transmits an output signal at an inverted second logic potential during and an active portion of a cycle. The equilibration circuit electrically isolates the first line and the second line and shorts the first line to the second line during and an inactive portion of the cycle. Upon completion of the inactive portion of the cycle, the first line and the second line have substantially equal starting potentials between the first logic potential and the second logic potential. Setting the starting potential between the first and second logic potentials shortens the delay associated with a transition between logic potentials. Additionally, one embodiment of the equilibration circuit selectively disconnects the amplifier from the power rails.
摘要翻译：提供了用于改善信号传播的系统和方法。中继器将传输线分割成第一和第二行。中继器包括反相放大器和平衡电路。反相放大器具有连接到第一线路的输入端和连接到第二线路的输出端。放大器接收第一逻辑电位的输入信号，并在循环的有效部分期间以反相的第二逻辑电位发送输出信号。平衡电路将第一线路和第二线路电隔离，并在该周期的非活动部分期间将第一线路短路到第二线路。在完成了该周期的无效部分之后，第一线路和第二线路具有在第一逻辑电位和第二逻辑电位之间具有基本相等的起始电位。设置第一和第二逻辑电位之间的起始电位会缩短与逻辑电位之间的转换相关的延迟。此外，平衡电路的一个实施例选择性地将放大器与电源轨分离。

84. 发明申请

US20020089367A1 Circuit configuration for supplying voltage to an integrated circuit via a pad 有权
标题翻译：用于通过焊盘向集成电路提供电压的电路配置
公开(公告)号：US20020089367A1
公开(公告)日：2002-07-11
申请号：US10066875
申请日：2002-02-04
发明人： Hans-Gerd Kirchhoff
IPC分类号： H03K019/0175 , H03K017/725
CPC分类号： G11C5/066 , Y10T307/724 , Y10T307/735 , Y10T307/858
摘要： A circuit configuration for supplying voltage to an integrated circuit via a pad that is connected to the input of a Schmitt trigger on the integrated circuit. The pad is also provided for configuring the integrated circuit. The integrated circuit has a multiplicity of voltage supply lines for voltage supply purposes. According to the invention, the pad is connected to a respective voltage supply line via a respective switch, and the switches are switched on or off by a control circuit that is controlled by at least one on-chip control signal.
摘要翻译：一种用于通过连接到集成电路上的施密特触发器的输入的焊盘向集成电路提供电压的电路配置。该垫还用于配置集成电路。集成电路具有用于电压供给目的的多个电源线。根据本发明，焊盘通过相应的开关连接到相应的电压供应线，并且开关由被至少一个片上控制信号控制的控制电路接通或断开。

85. 发明申请

US20020089350A1 Dual rail power supply sequence tolerant off-chip driver 有权
标题翻译：双轨供电顺序容许片外驱动
公开(公告)号：US20020089350A1
公开(公告)日：2002-07-11
申请号：US09758054
申请日：2001-01-10
申请人： International Business Machines Corporation
发明人： Anthony Correale JR. , Terry Cain Coughlin JR. , Douglas Willard Stout
IPC分类号： H03K019/0175
CPC分类号： H03K19/00315
摘要： The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.
摘要翻译：本发明的保护电路解决了由两电源CMOS集成电路中的一个电源的损耗引起的不确定的逻辑电平的问题。本发明的电路取代了电源排序的典型方案来解决问题。本文所公开的电路检测核心电压的状态，并且当核心电压被检测为关闭时，禁用输出驱动器。禁用的驱动器处于高阻抗状态，从而消除了损坏的可能性，并消除了对电源排序的需要。本发明还可以防止在正常工作期间集成电路核心电压VDD，电源的突然损失。

86. 发明申请

US20020075035A1 Circuit for providing a logical output signal in accordance with crossing points of differential signals 有权
标题翻译：用于根据差分信号的交叉点提供逻辑输出信号的电路
公开(公告)号：US20020075035A1
公开(公告)日：2002-06-20
申请号：US09957922
申请日：2001-09-21
发明人： Bernhard Roth
IPC分类号： H03K019/0175
CPC分类号： H03K19/00323 , G01R31/31924 , G01R31/31937 , H03K5/2418
摘要： Disclosed is a circuit (FIG. 6a) for providing a logical output signal (OUTD) in accordance with crossing points of a differential signal, whereby the logical output signal (OUTD) has a first logical level (high) and a second logical level (low), the differential signal comprises a normal input signal (SIG) and a complementary input signal (NSIG) as the complementary signal to the normal input signal (SIG), and the crossing points occur when the normal input signal (SIG) and the complementary input signal (NSIG) have the same level. The circuit comprises a first amplifier (C1) for amplifying a first signal difference between the normal input signal (SIG) and a first threshold value (TH1), and for providing as a first output signal (SIGOUT) the amplified first signal difference, and a second amplifier (C2) for amplifying a second signal difference between the complementary input signal (NSIG) and a second threshold value (TH2), and for providing as a second output signal (NSIGOUT) the amplified second signal difference, whereby the first and the second threshold values are set to the same level (VTHnullTH1nullTH2). The circuit further comprises a first comparator (C3) for providing the first logical level (high) when a third signal difference between the first output signal (SIGOUT) and the second output signal (NSIGOUT) is greater than a third threshold value (VTH3), and for providing the second logical level (low) when the third signal difference is smaller than the third threshold value.
摘要翻译：公开了一种用于根据差分信号的交叉点提供逻辑输出信号（OUTD）的电路（图6a），由此逻辑输出信号（OUTD）具有第一逻辑电平（高）和第二逻辑电平低），差分信号包括作为与正常输入信号（SIG）的互补信号的正常输入信号（SIG）和互补输入信号（NSIG），并且当正常输入信号（SIG）和互补输入信号（NSIG）具有相同的电平。该电路包括用于放大正常输入信号（SIG）和第一阈值（TH1）之间的第一信号差的第一放大器（C1），以及用于提供放大的第一信号差的第一输出信号（SIGOUT），以及用于放大互补输入信号（NSIG）和第二阈值（TH2）之间的第二信号差的第二放大器（C2），以及用于提供放大的第二信号差的第二输出信号（NSIGOUT），由此第一和第二阈值被设置为相同的电平（VTH = TH1 = TH2）。该电路还包括第一比较器（C3），用于当第一输出信号（SIGOUT）和第二输出信号（NSIGOUT）之间的第三信号差大于第三阈值（VTH3）时提供第一逻辑电平（高）并且当第三信号差小于第三阈值时提供第二逻辑电平（低）。

87. 发明申请

US20020070757A1 Buffer circuit for the reception of a clock signal 有权
标题翻译：用于接收时钟信号的缓冲电路
公开(公告)号：US20020070757A1
公开(公告)日：2002-06-13
申请号：US09935292
申请日：2001-08-22
申请人： STMicroelectronics S.A.
发明人： Francesco La Rosa
IPC分类号： H03K019/0175
CPC分类号： G11C7/225 , G11C7/22 , H03K19/00361
摘要： A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitive to a supply voltage of the buffer circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered.
摘要翻译：缓冲电路包括用于接收逻辑信号的输入端和用于将逻辑信号从输入传送到缓冲电路的输出的传送电路。传输电路包括至少一个具有对缓冲电路的电源电压敏感的跳变点的逻辑门。缓冲电路还包括传送电路，用于在逻辑信号具有后沿和/或前沿时传送具有预定持续时间的禁止信号;以及禁止电路，用于禁止传输电路并将缓冲电路的输出与当禁止信号被传送时缓冲电路的输入。当禁止信号被传送时，存储电路保持在缓冲电路的输出处的逻辑信号的逻辑值。

88. 发明申请

US20020067079A1 Modulated input signal filter 有权
标题翻译：调制输入信号滤波器
公开(公告)号：US20020067079A1
公开(公告)日：2002-06-06
申请号：US09728191
申请日：2000-12-01
发明人： Pieter Schieke , Steven Dawson
IPC分类号： H03K019/0175
CPC分类号： H03K9/08 , Y10T307/766
摘要： A modulated input signal is filtered to reduce noise. The state of the input signal controls the state of a switch. Depending upon its state, the switch connects one of two circuits to a gate. The gate receives the input signal and it passes or blocks the signal depending upon the state of the signal received from the switched circuits. When it is passing the input signal, the output of the gate is equivalent to the input signal. When it is blocking the input signal, the output of the gate is set to a default state. The default state is independent of the input signal. One of the switched circuits gradually modifies the signal provided by the gate to allow the input signal to pass through. The other switched circuit gradually modifies the signal provided to the gate to block the input signal.
摘要翻译：调制输入信号被滤波以减少噪声。输入信号的状态控制开关的状态。根据其状态，开关将两个电路中的一个连接到门。门接收输入信号，并根据从开关电路接收的信号的状态通过或阻止信号。当通过输入信号时，门的输出等同于输入信号。当阻塞输入信号时，门的输出被设置为默认状态。默认状态与输入信号无关。一个开关电路逐渐地修改由门提供的信号以允许输入信号通过。另一个开关电路逐渐修改提供给门的信号以阻止输入信号。

89. 发明申请

US20020063580A1 Digital level adjustment 有权
标题翻译：数字电平调整
公开(公告)号：US20020063580A1
公开(公告)日：2002-05-30
申请号：US09989961
申请日：2001-11-21
发明人： Rainer Esch
IPC分类号： H03K019/0175
CPC分类号： H03K19/0016 , H03K19/00361
摘要： Apparatuses for level adjustment are essential to make adjustments to signals between integrated circuits having differing signal levels in electronic circuits. To assure signal adjustment for a large number of signals, as occur in parallel busses, an apparatus for level adjustment is used. This digital level adjustment uses the I/O cells already present in the integrated circuits with an externally wired pullup resistor and an internal digitally programmed or constructed signal connection for controlling output drivers.
摘要翻译：用于电平调节的装置对于在电子电路中具有不同信号电平的集成电路之间的信号进行调整是至关重要的。为了确保在并行总线中发生的大量信号的信号调整，使用用于电平调整的装置。该数字电平调整使用已经存在于集成电路中的I / O单元，其具有外部布线的上拉电阻器和用于控制输出驱动器的内部数字编程或构造的信号连接。

90. 发明申请

US20020057107A1 Capacitively coupled re-referencing circuit with transient correction 失效
标题翻译：具有瞬态校正的电容耦合重新参考电路
公开(公告)号：US20020057107A1
公开(公告)日：2002-05-16
申请号：US10040124
申请日：2002-01-04
发明人： Jiann-Neng Chen
IPC分类号： H03K019/0175
CPC分类号： H03K19/017509 , H03K5/007
摘要： A re-referencing circuit for re-referencing a digital input signal from a first logic environment to a second logic environment includes a non-inverting circuit having a non-inverting transfer characteristic between the input and the output. A capacitive element has a first node coupled to the input of the non-inverting circuit and a second node arranged to receive the digital input signal. A resistive element is coupled between the input and the output of the non-inverting circuit. The re-referencing circuit further includes a transient correcting circuit having a first input coupled to a substantially DC level of the first logic environment, a second input coupled to a substantially DC level of the second logic environment, and an output coupled to the input of the non-inverting circuit. The transient correcting circuit applies transient DC differences between the two environments to cancel the effects of transients in the digital input signal.
摘要翻译：用于将从第一逻辑环境到第二逻辑环境的数字输入信号重新参考的重新参考电路包括在输入和输出之间具有非反相传输特性的非反相电路。电容元件具有耦合到非反相电路的输入端的第一节点和布置成接收数字输入信号的第二节点。电阻元件耦合在非反相电路的输入和输出之间。重新参考电路还包括瞬态校正电路，其具有耦合到第一逻辑环境的基本上DC电平的第一输入，耦合到第二逻辑环境的基本上DC电平的第二输入，以及耦合到非反相电路。瞬态校正电路在两种环境之间施加瞬态DC差异，以消除数字输入信号瞬变的影响。

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