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81. 发明申请

US20040238970A1 Electronic pckage with conductive pad capable of withstanding significant loads and information handling system utilizing same 审中-公开
标题翻译：具有能够承受显着负载的导电焊盘的电子印章和利用其的信息处理系统
公开(公告)号：US20040238970A1
公开(公告)日：2004-12-02
申请号：US10868066
申请日：2004-06-16
申请人： Endicott Interconnect Technologies, Inc.
发明人： David J. Alcoe
IPC分类号： H01L023/48
CPC分类号： H01L23/49838 , H01L23/49811 , H01L23/49822 , H01L2224/16225 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/15312 , H05K1/113 , H05K1/114 , H05K1/115 , H05K1/116 , H05K3/3426 , H05K3/4602 , H05K2201/09454 , H05K2201/09472 , H05K2201/09509 , H05K2201/0979 , H05K2201/10318 , H01L2224/0401
摘要： A circuitized substrate which utilizes an underlying conductive layer coupled to a pad on the substrate to assure a reinforced pad which will not be damaged or removed from the substrate when subjected to a significant load. Two or more pads can be similarly provided and coupled to the conductive layer, e.g., the layer being a common (ground) layer. An information handling system (e.g., a personal computer) utilizing the substrate is also provided.
摘要翻译：电路化基板，其利用与基板上的焊盘耦合的下层导电层，以确保在经受显着载荷时不会损坏或从基板移除的加强垫。可以类似地提供两个或更多个焊盘并耦合到导电层，例如该层是公共（接地）层。还提供了利用该基板的信息处理系统（例如个人计算机）。

82. 发明申请

US20040238211A1 Circuit board, circuit board mounting method, and electronic device using the circuit board 审中-公开
标题翻译：电路板，电路板安装方法以及使用电路板的电子设备
公开(公告)号：US20040238211A1
公开(公告)日：2004-12-02
申请号：US10474427
申请日：2004-06-17
发明人： Yuki Momokawa , Eiichi Kono , Masaru Saitou , Kazuhiko Tanabe
IPC分类号： H05K001/11 , H05K003/34
CPC分类号： H05K3/3426 , H05K1/0201 , H05K1/09 , H05K1/114 , H05K3/0094 , H05K3/3415 , H05K3/3421 , H05K3/3452 , H05K3/3463 , H05K3/3468 , H05K3/3494 , H05K3/42 , H05K3/429 , H05K2201/062 , H05K2201/09263 , H05K2201/09572 , H05K2201/09727 , H05K2201/10909 , H05K2201/2054 , H05K2203/0191 , H05K2203/047 , H05K2203/081 , H05K2203/1105 , H05K2203/1121 , H05K2203/1394 , H05K2203/304 , Y02P70/613 , Y10T29/49144
摘要： A through hole 2 in a circuit board 1 and to be joined to a lead 5 in a surface mounting component 6 is prepared from a material such as nickel, and palladium having a thermal conductivity equal to or less than 100 W/m.K, the circuit board 1 involving a alloy layer composed of at least a member selected from elements of solder 8, a pad 7, and the lead 5 in a solder joined site of the lead 5 and the pad 7, whereby a quantity of heat transmitted to the joined site via the through hole 2 is reduced at the time when wave-soldering is applied to the back of the circuit board 1 after the surface mounting component 6 was mounted, so that the joined site is maintained at a temperature equal to or less than a melting point of the alloy layer, and hence, exfoliation in an interface of the joined site is prevented, and reliability in the joint of the lead 5 and the pad 7 is elevated.
摘要翻译：电路板1中的通孔2并且与表面安装部件6中的引线5接合，由诸如镍的材料和热导率等于或小于100W / mK的钯制成，电路板1，其包括在引线5和焊盘7的焊料接合部位中至少由焊料8，焊盘7和引线5的元件组成的合金层，由此传递到接合部在安装表面安装部件6之后，当在电路板1的背面上施加波峰焊时，通过通孔2的位置被减小，使得接合部位保持在等于或小于合金层的熔点，因此防止了接合部位的界面的剥离，引线5和焊盘7的接头的可靠性提高。

83. 发明授权

US06809935B1 Thermally compliant PCB substrate for the application of chip scale packages 有权
标题翻译：耐热兼容的PCB基板，用于应用芯片级封装
公开(公告)号：US06809935B1
公开(公告)日：2004-10-26
申请号：US09684519
申请日：2000-10-10
申请人： Jin-Yuan Lee
发明人： Jin-Yuan Lee
IPC分类号： H05K710
CPC分类号： H01L23/3735 , H01L23/49816 , H01L23/49822 , H01L24/45 , H01L24/48 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/00015 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181 , H01L2924/30107 , H05K1/0271 , H05K1/113 , H05K1/114 , H05K3/4626 , H05K3/4688 , H05K7/1061 , H05K2201/0133 , H05K2201/09436 , H05K2201/10734 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399 , H01L2224/0401 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A new method is provided for mounting a semiconductor on the surface of a Printed Circuit Board. A layer of Elastomer is deposifed on the surface face of the PCB, this layer of Elastomer makes the PCB into a thermally compliant PCB such that the thermal mismatch between the PCB and the semiconductor die that is mounted on the PCB is sharply reduced. Openings are created in the layer of Elastomer and electrical interfaces are created such that the PCB can be connected to the semiconductor die that is mounted on the PCB.
摘要翻译：提供了一种用于将半导体安装在印刷电路板的表面上的新方法。一层弹性体在PCB的表面上被剥离，该层的弹性体使得PCB成为热兼容的PCB，使得PCB和安装在PCB上的半导体管芯之间的热失配急剧减少。在弹性体层中形成开口，并且创建电接口，使得PCB可以连接到安装在PCB上的半导体管芯。

84. 发明授权

US06803658B2 Substrate with top-flattened solder bumps and method for manufacturing the same 失效
标题翻译：具有顶部扁平焊料凸块的基板及其制造方法
公开(公告)号：US06803658B2
公开(公告)日：2004-10-12
申请号：US10755379
申请日：2004-01-13
申请人： Tomoe Suzuki
发明人： Tomoe Suzuki
IPC分类号： H01L2348
CPC分类号： H05K3/3457 , H01L21/4853 , H01L2224/0401 , H01L2224/06102 , H01L2224/1403 , H05K1/114 , H05K3/3484 , H05K3/4602 , H05K2201/09736 , H05K2203/0278 , H05K2203/043
摘要： A wiring substrate includes a solid layer formed on the core substrate to partially cover the same. At least one resin dielectric layer is formed on the solid layer and the core substrate while a plurality of pads are formed on the resin dielectric layer and are exposed at the main surface of the wiring substrate. First pads are located within a region above the solid layer and second pads located outside of that region. First top-flattened solder bumps are formed on the first pads and second top-flattened solder bumps are formed on the second pads. The bumps all include a top face of the same diameter.
摘要翻译：布线基板包括形成在芯基板上以部分地覆盖其的固体层。在固体层和芯基板上形成至少一个树脂电介质层，同时在树脂电介质层上形成多个焊盘并在布线基板的主表面露出。第一焊盘位于固体层上方的区域内，第二焊盘位于该区域的外部。在第一焊盘上形成第一顶部扁平化的焊料凸块，并且在第二焊盘上形成第二顶部扁平化的焊料凸块。这些凸块都包括相同直径的顶面。

85. 发明授权

US06754057B2 Capacitor damage arrestor 有权
标题翻译：电容器损坏避雷器
公开(公告)号：US06754057B2
公开(公告)日：2004-06-22
申请号：US09967763
申请日：2001-09-29
申请人： Robert A. Pereira , D. Joseph Stoddard
发明人： Robert A. Pereira , D. Joseph Stoddard
IPC分类号： H01G212
CPC分类号： H05K1/0201 , H05K1/0231 , H05K1/114 , H05K2201/093 , H05K2201/09309 , H05K2201/0969 , H05K2201/10636 , Y02P70/611
摘要： A method for mounting a component on an assembly is provided, such as to prevent shorting between a voltage plane and a ground plane that may be caused when the component fails and generates temperature rises that result in insulation failure. The method includes removing a section of one or more of the group including a ground plane and a voltage plane in an area of the component, where the area of the section is selected to prevent damage to the component that can be caused by shorting between the ground plane and the voltage plane if insulation failure occurs.
摘要翻译：提供了一种用于将组件安装在组件上的方法，以防止在组件故障时可能引起的电压平面和接地面之间的短路，并产生导致绝缘失效的温度上升。该方法包括在组件的区域中去除包括接地平面和电压平面的该组中的一个或多个的部分，其中选择该部分的区域以防止可能由于部件之间的短路而导致的部件损坏如果发生绝缘故障，接地层和电压平面。

86. 发明申请

US20040104465A1 Wiring board and a packaging assembly using the same 失效
标题翻译：接线板和使用其的包装组件
公开(公告)号：US20040104465A1
公开(公告)日：2004-06-03
申请号：US10676732
申请日：2003-09-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takeshi Kusakabe , Isao Ozawa
IPC分类号： H01L023/58 , H05K007/06
CPC分类号： H01L24/06 , H01L23/49822 , H01L23/50 , H01L23/522 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/3025 , H05K1/0218 , H05K1/114 , H05K2201/0715 , H05K2201/09336 , H05K2201/10734 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A wiring board includes an insulating board defined by a first surface and a second surface opposing to the first surface; first signal strips disposed on the first surface; a first power distribution plane provided on the first surface so as to occupy a residual area of the first signal strips; lands disposed on the second surface; via metals penetrating the insulating board so as to connect the lands to the corresponding first signal strips; a second power distribution plane provided on the second surface.
摘要翻译：布线板包括由第一表面和与第一表面相对的第二表面限定的绝缘板; 设置在第一表面上的第一信号条; 设置在所述第一表面上以占据所述第一信号条的剩余区域的第一配电平面; 设置在第二表面上的土地; 通过穿过绝缘板的金属，以将焊盘连接到相应的第一信号条; 设置在第二表面上的第二配电平面。

87. 发明申请

US20040047570A1 Circuit board construction for use in small form factor fiber optic communication system transponders 失效
标题翻译：电路板结构用于小尺寸光纤通信系统应答器
公开(公告)号：US20040047570A1
公开(公告)日：2004-03-11
申请号：US10237384
申请日：2002-09-06
申请人： PARACER, INC.
发明人： WeiZen Lo , Henju Cheng , William Wang
IPC分类号： G02B006/42
CPC分类号： G02B6/3897 , H05K1/114 , H05K2201/09227 , H05K2201/10189 , H05K2201/10545 , H05K2201/10734
摘要： A transponder assembly for use with fiber optic digital communication cables having multiple parallel optic fiber elements. The transponder assembly features separate transmitter port and receiver ports and an electrical connector for connecting with computer or communication systems. The transponder assembly includes a parallel optic transmitter module and a parallel optic receiver module. The assembly also includes a circuit board on which a semiconductor chip useful for signal processing and the electrical connector are mounted. A Flex circuit is used in connecting the circuit board to the parallel optic modules. The semiconductor chip and electrical connector are mounted directly across from one another on opposite surfaces of the circuit board using ball grid arrays having overlapping attachment structures.
摘要翻译：一种用于具有多个平行光纤元件的光纤数字通信电缆的应答器组件。应答器组件具有单独的发射器端口和接收器端口以及用于与计算机或通信系统连接的电连接器。应答器组件包括并行光发射器模块和并行光接收器模块。组件还包括其上安装用于信号处理的半导体芯片和电连接器的电路板。 Flex电路用于将电路板连接到并行光模块。半导体芯片和电连接器使用具有重叠的附接结构的球栅阵列彼此直接地安装在电路板的相对表面上。

88. 发明申请

US20040021232A1 FLIP-CHIP BALL GRID ARRAY PACKAGE FOR ELECTROMIGRATION TESTING 有权
标题翻译：用于电气测试的片芯球网阵列包装
公开(公告)号：US20040021232A1
公开(公告)日：2004-02-05
申请号：US10212448
申请日：2002-08-05
发明人： Senol Pekin , Anand Govind , Carl Iwashita
IPC分类号： H01L023/48
CPC分类号： H01L22/34 , H01L23/49816 , H01L2924/15174 , H05K1/0268 , H05K1/114 , H05K2201/10674
摘要： A test package for electromigration testing includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed on the I/O pads, and a substrate having a plurality of bump-to-bump interconnects formed on a top surface of the substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.
摘要翻译：用于电迁移测试的测试封装包括具有形成在金属层上的多个I / O焊盘的芯片，形成在芯片上的多个迹线，电连接相邻的I / O焊盘对，多个凸起互连 I / O焊盘和具有多个凸块到凸块互连的衬底，该衬底形成在与裸片相邻的衬底的顶表面上，其中多个凸块到凸块互连电耦合到多个凸起的互连，因此多个凸起的互连串联连接。

89. 发明申请

US20040016570A1 Substrate and method of manufacturing the same 审中-公开
标题翻译：基材及其制造方法
公开(公告)号：US20040016570A1
公开(公告)日：2004-01-29
申请号：US10450182
申请日：2003-06-10
发明人： Reo Yamamoto , Yoshihide Yamamoto
IPC分类号： H05K001/00 , H01R012/04 , H05K003/02
CPC分类号： H01L23/49811 , H01L23/15 , H01L23/49827 , H01L2924/0002 , H05K1/0206 , H05K1/0306 , H05K1/114 , H05K3/0008 , H05K3/0082 , H05K3/064 , H05K3/246 , H05K3/4061 , H05K2201/0317 , H05K2201/0347 , H05K2201/10674 , H05K2203/167 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： It is an object to provide a method of efficiently manufacturing a double-sided circuit board having a metallic via hole which can suitably be used as a submount for mounting a semiconductor device, that is, a substrate in which the electrical contact of a metallic via hole and a circuit pattern is excellent and an element can easily be bonded and positioned. In a ceramic substrate having a via hole filled with a conductive material, a ceramic portion of at least one of faces of the ceramic substrate has a surface roughness of Ranull0.8 nullm, a substrate in which the conductive material filled in the via hole present on at least one of the faces is protruded from a surface of the face with a height of 0.3 to 5.0 nullm is used as a material substrate and a conductive layer is formed on the surface, and subsequently, the conductive layer is patterned and a solder film pattern for element mounting is formed based on a position of a convex portion of the conductive layer which results from the via hole present on an underlaid portion of the conductive layer.
摘要翻译：本发明的目的是提供一种有效地制造具有金属通孔的双面电路板的方法，该金属通孔适合地用作安装半导体器件的基座，即其中金属通孔孔和电路图案是优异的，元件可以容易地粘合和定位。在具有填充有导电材料的通路孔的陶瓷基板中，陶瓷基板的表面的至少一面的陶瓷部分的表面粗糙度Ra <0.8μm，其中填充在通孔中的导电材料存在于至少一个面上的表面的表面的高度为0.3〜5.0μm的面的表面被用作材料基板，并且在表面上形成导电层，接着，对导电层进行图案化和基于存在于导电层的底层部分上的通孔产生的导电层的凸部的位置形成用于元件安装的焊料膜图案。

90. 发明授权

US06660942B2 Semiconductor device with an exposed external-connection terminal 失效
标题翻译：具有暴露的外部连接端子的半导体器件
公开(公告)号：US06660942B2
公开(公告)日：2003-12-09
申请号：US09826512
申请日：2001-04-05
申请人： Michio Horiuchi , Takashi Kurihara
发明人： Michio Horiuchi , Takashi Kurihara
IPC分类号： H05K103
CPC分类号： H05K3/4694 , H01L23/3735 , H01L23/49822 , H01L23/49894 , H01L2224/05567 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2224/73204 , H01L2924/01078 , H01L2924/01079 , H05K1/0271 , H05K1/114 , H05K3/4652 , H05K3/4655 , H05K2201/0133 , H05K2201/0187 , H05K2201/0195 , H05K2201/09972 , Y10T428/24942 , Y10T428/2495 , H01L2924/00014
摘要： A wiring substrate equipped with a rerouted wiring having one end connected to an electronic-part mounting pad for electrically connecting an electronic part and another end connected to an external-connection terminal. In the wiring substrate, a low-elasticity underlayer made of a material having a lower modulus of elasticity than that of a base material of the wiring substrate is disposed between the base material of the wiring substrate and each of the electronic-part mounting pad and the rerouted wiring. A method of manufacturing the wiring substrate and a semiconductor device using the wiring substrate are also disclosed.
摘要翻译：一种布线基板，其配备有重新布线的布线，其一端连接到用于电连接电子部件的电子部件安装焊盘和连接到外部连接端子的另一端。在布线基板中，在布线基板的基材和电子部件安装用基板的每一个之间配置有由比布线基板的基材低的弹性模量的材料制成的低弹性底层，重新布线。还公开了制造布线基板的方法和使用该布线基板的半导体器件。

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