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81. 发明申请

US20070064836A1 Format efficient timing acquisition for magnetic recording read channels 有权
标题翻译：为磁记录读通道格式化高效的定时采集
公开(公告)号：US20070064836A1
公开(公告)日：2007-03-22
申请号：US11228762
申请日：2005-09-16
申请人： Jason Byrne , German Feyh , Jeffrey Grundvig , Aravind Nayak , Richard Rauschmayer
发明人： Jason Byrne , German Feyh , Jeffrey Grundvig , Aravind Nayak , Richard Rauschmayer
IPC分类号： H04L27/00 , H03D3/24 , H04L7/00
CPC分类号： H04L7/0054 , H04L7/0004 , H04L2007/047
摘要： A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.
摘要翻译：一种使用前置码同步位的磁记录应用的定时恢复电路。定时恢复电路使用具有数字旋转器的经修改的数字锁相环。模数转换器（ADC）接收模拟输入，并向数字旋转器提供ADC数字采样。为了补偿模拟延迟和回转，应注意，改变ADC中的采样点等同于在输出中引入相位变化。例如，使用数字旋转器可以比通过改变模拟采样点更快地数字地引入该相位变化。与改变ADC采样点所需的时间相比，数字旋转器几乎瞬间捕捉到初始相位估计。当ADC转换到初始相位估计时，数字旋转器将逐步退化，直到ADC达到初始相位估计。

82. 发明申请

US20070038789A1 Dynamic bus inversion method and system 有权
标题翻译：动态总线反演方法及系统
公开(公告)号：US20070038789A1
公开(公告)日：2007-02-15
申请号：US11357291
申请日：2006-02-17
申请人： Joseph Macri , Stephen Morein , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Ming-Ju Lee , Lin Chen
IPC分类号： G06F13/42
CPC分类号： H04L25/4915 , H03L7/07 , H03L7/0805 , H03L7/0814 , H04L7/0004 , H04L7/0008 , H04L7/0037 , H04L7/0337
摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.
摘要翻译：描述了动态总线反演（DBI）方法和系统。在各种实施例中，发射机通过多比特高速总线向接收机发送数据。在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。

83. 发明授权

US07099424B1 Clock data recovery with selectable phase control 有权
标题翻译：时钟数据恢复，可选择相位控制
公开(公告)号：US07099424B1
公开(公告)日：2006-08-29
申请号：US09941079
申请日：2001-08-28
申请人： Kun-Yung K. Chang , Jason C. Wei , Donald V. Perino
发明人： Kun-Yung K. Chang , Jason C. Wei , Donald V. Perino
IPC分类号： H04L25/38
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0814 , H03L7/089 , H03L7/091 , H04L7/0004 , H04L7/0337 , H04L7/10
摘要： A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.
摘要翻译：一种用于从输入信号恢复时钟信号和数据信号的时钟数据恢复（CDR）电路。 CDR电路包括控制电路，选择电路和相位调整电路。控制电路根据输入信号和第一时钟信号之间的相位关系产生第一控制信号。耦合选择电路以从控制电路接收第一控制信号并耦合以接收第二控制信号。选择电路响应于选择信号来选择要输出的第一控制信号或第二控制信号作为选择的控制信号。相位调整电路被耦合以从选择电路接收所选择的控制信号，相位调整电路响应所选择的控制信号来调节第一时钟信号的相位。

84. 发明授权

US07042854B2 Method and apparatus for acquiring a synchronization signal 有权
公开(公告)号：US07042854B2
公开(公告)日：2006-05-09
申请号：US09768726
申请日：2001-01-24
申请人： Bassel Beidas , Olga Ritterbush , Stanley Kay , Yezdi Antia , Bala Subramaniam
发明人： Bassel Beidas , Olga Ritterbush , Stanley Kay , Yezdi Antia , Bala Subramaniam
IPC分类号： H04B7/212
CPC分类号： H04J3/0611 , H04B7/2125 , H04L7/0004
摘要： A method and system for acquiring a time division multiplexed synchronization signal in a satellite communication system is provided. The signal is provided as a series of frames with beacon signals time division multiplexed into at least one time slot of each frame. The beacon signal in each frame comprises a unique word sequence, which is the same in each frame, and a portion of a PN sequence. The entire PN sequence is distributed into a plurality of frames forming a superframe. Initially, the power level of the incoming signal is determined by locating the maximum power received in half time slot intervals. Next a series of frames are correlated against the expected unique word, each at one of a plurality of possible frequencies. The frequency generating the maximum correlation with the unique word is selected. The frequency is fine tuned by comparing the actual arrival time of the unique word in each frame with the estimated arrival time based on the current frequency, and adjusting the frequency accordingly. Also, the start of the superframe is located by correlating the PN sequence portion of each beacon signal against a known PN sequence until a match is found. Once the frequency offset is reduced below a threshold value, and the start of the PN sequence of the incoming signal is located, acquisition is completed.

85. 发明授权

US07006590B2 Timing circuit with dual phase locked loops 有权
公开(公告)号：US07006590B2
公开(公告)日：2006-02-28
申请号：US09865504
申请日：2001-05-29
申请人： Simon Skierszkan , Robert van der Valk
发明人： Simon Skierszkan , Robert van der Valk
IPC分类号： H03D3/24 , H04B1/38 , H04L25/00
CPC分类号： H03L7/07 , H03L7/23 , H03L2207/50 , H04L7/0004 , H04L7/033
摘要： A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.

86. 发明授权

US06990160B1 Reception apparatus and method 失效
标题翻译：接收装置和方法
公开(公告)号：US06990160B1
公开(公告)日：2006-01-24
申请号：US09661306
申请日：2000-09-13
申请人： Katsuaki Abe , Masayuki Orihashi , Job Cleopa Msuya , Morikazu Sagawa , Masayoshi Yoneyama
发明人： Katsuaki Abe , Masayuki Orihashi , Job Cleopa Msuya , Morikazu Sagawa , Masayoshi Yoneyama
IPC分类号： H04L7/00
CPC分类号： H04L7/042 , H04L7/0004 , H04L7/007 , H04L7/0334
摘要： A phase of a sampling clock provided from clock generating circuit 107 is switched periodically and alternately with a phase difference of 180 degrees, and during a period of each phase, timing estimating circuit 105 estimates a symbol timing. High-accuracy timing estimating circuit 109 selects an estimated result with higher reliability among symbol timing estimated results obtained in respective periods, thereby enabling estimation of the symbol timing with time resolution twice a sampling period. It is possible to decrease an operation frequency in an A/D conversion circuit even in a system requiring timing synchronization accuracy with high accuracy.
摘要翻译：从时钟发生电路107提供的采样时钟的相位以180度的相位差周期性地交替地切换，并且在每个相位的周期期间，定时估计电路105估计符号定时。高精度定时估计电路109在各周期中获得的符号定时估计结果中选择具有更高可靠性的估计结果，从而能够以采样周期的两倍的时间分辨率估计符号定时。即使在需要高精度的定时同步精度的系统中也可以降低A / D转换电路的工作频率。

87. 发明授权

US06961862B2 Drift tracking feedback for communication channels 有权
标题翻译：用于通信通道的漂移跟踪反馈
公开(公告)号：US06961862B2
公开(公告)日：2005-11-01
申请号：US10802634
申请日：2004-03-17
申请人： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
发明人： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
IPC分类号： G06F1/04 , H04L7/00 , H04L7/10 , H04L25/14
CPC分类号： G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0004 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14
摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
摘要翻译：通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。通信链路耦合第一和第二组件。校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要响应监控功能。

88. 发明申请

US20050232218A1 Low-power operation of systems requiring low-latency and high-throughput 审中-公开
标题翻译：需要低延迟和高吞吐量的系统的低功耗操作
公开(公告)号：US20050232218A1
公开(公告)日：2005-10-20
申请号：US11044117
申请日：2005-01-27
申请人： Bruce Edwards , Mark Matson , Walter Morton , Jay Pattin
发明人： Bruce Edwards , Mark Matson , Walter Morton , Jay Pattin
IPC分类号： H04B7/212 , H04L7/00 , H04L12/28 , H04L12/56
CPC分类号： G06F1/3203 , G06F1/324 , H04L7/0004 , H04W52/029 , H04W56/00 , Y02D10/126 , Y02D70/122 , Y02D70/142 , Y02D70/144
摘要： A method and apparatus for providing multiple clock signals for a communication device, with the clock signals being generated to correspond to the operating mode of various core modules of the communication device. A clock generator is operable to generate a plurality of clock signals having performance characteristics corresponding to the operating mode of individual cores in the system. A clock management logic circuit is operable to receive a plurality of request signals from the core modules and to cause the clock generator to generate appropriate clock signals based on the requests and other information relating to the operating mode of the core modules.
摘要翻译：一种用于为通信设备提供多个时钟信号的方法和装置，其中生成时钟信号以对应于通信设备的各种核心模块的操作模式。时钟发生器可操作以产生具有与系统中各个核的操作模式对应的性能特征的多个时钟信号。时钟管理逻辑电路可操作以从核心模块接收多个请求信号，并且使得时钟发生器基于与核心模块的操作模式有关的请求和其他信息来产生适当的时钟信号。

89. 发明申请

US20050218999A1 Burst mode clock and data recovery frequency calibration 有权
标题翻译：突发模式时钟和数据恢复频率校准
公开(公告)号：US20050218999A1
公开(公告)日：2005-10-06
申请号：US10814250
申请日：2004-04-01
申请人： Hrvoje Jasa , Gary Polhemus , Kenneth Snowdon
发明人： Hrvoje Jasa , Gary Polhemus , Kenneth Snowdon
IPC分类号： H03L7/00 , H03L7/089 , H03L7/14 , H04L7/00 , H04L7/033
CPC分类号： H03L7/141 , H03L7/089 , H04L7/0004 , H04L7/0083 , H04L7/033
摘要： A direct calibration technique significantly tightens a tolerance band between multiple voltage controlled oscillators (VCOs), to correct for slight frequency mismatch between the multiple VCOs. The tightened tolerance band enhances the bit error rate (BER) and/or lengthens the possible consecutive identical digits (CIDs) length, and is particularly useful in integrated circuit applications. A Frequency Locked Loop (FLL), an accumulator, and a DAC are implemented to form a calibration loop that becomes far more digital in nature than a PLL, permitting greater embedded circuit test coverage and ease of integration in VLSI digital technologies. A frequency calibrated loop with digital accumulator and DAC in lieu of a PLL with associated charge pump integrator eliminates the need for large integrated capacitors, sensitivity to drift due to the leakage currents associated with deep sub-micron technologies, and embedded analog voltages which generally cannot be tested.
摘要翻译：直接校准技术显着收紧了多个压控振荡器（VCO）之间的容差带，以纠正多个VCO之间轻微的频率失配。加密的容限带增强了误码率（BER）和/或延长了可能的连续相同数字（CID）长度，并且在集成电路应用中特别有用。实现了频率锁定环（FLL），累加器和DAC，以形成一种比PLL更具数字化的校准环路，从而允许更大的嵌入式电路测试覆盖率和易于集成的VLSI数字技术。具有数字累加器和DAC的频率校准回路代替具有相关电荷泵积分器的PLL，无需大型集成电容器，由于与深亚微米技术相关的漏电流导致的漂移敏感性，以及通常不能使用的嵌入式模拟电压被测试。

90. 发明申请

US20050190798A1 RF door activation system 失效
标题翻译：射频门激活系统
公开(公告)号：US20050190798A1
公开(公告)日：2005-09-01
申请号：US11051310
申请日：2005-02-04
申请人： Phong Chau , Raymond Benson
发明人： Phong Chau , Raymond Benson
IPC分类号： G06F7/04 , G07C9/00 , H04L7/00 , H04L7/04 , H04L7/10
CPC分类号： G07C9/00182 , G07C2009/00793 , G07C2009/00928 , G07C2209/08 , H04L7/0004 , H04L7/0012 , H04L7/041 , H04L7/10
摘要： The present invention provides a radio frequency (“RF”) activation system with improved operating capability and ease of installation. Improved responsiveness is provided by the receiver which determines the frame timing of incoming signals and calculates the estimated time of arrival for ensuing frames thus minimizing loss of frame synchronization problems. In one embodiment, this is accomplished by determining the time span of the frame start sequence and using this to determine the frame timing of an incoming RF signal. The receiver also makes corrections for timing errors between the receiver and transmitter by re-synchronizing the receiver with the incoming RF signal.
摘要翻译：本发明提供了具有改进的操作能力和易于安装的射频（“RF”）激活系统。由接收机提供改善的响应性，该接收机确定输入信号的帧定时，并计算随后的帧的估计到达时间，从而最大限度地减少帧同步问题的丢失。在一个实施例中，这是通过确定帧起始序列的时间间隔并使用其来确定输入RF信号的帧定时来实现的。接收机还通过将接收机与输入的RF信号重新同步来对接收机和发射机之间的定时误差进行校正。

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