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81. 发明授权

US06275179B1 Digital to analog converter using a current matrix system 失效
标题翻译：使用电流矩阵系统的数模转换器
公开(公告)号：US06275179B1
公开(公告)日：2001-08-14
申请号：US09358368
申请日：1999-07-21
申请人： Hiroyuki Mori
发明人： Hiroyuki Mori
IPC分类号： H03M166
CPC分类号： H03M1/068 , H03M1/742
摘要： A first current cell group of an digital-to-analog converter has a first set of current cells which individually turn on and off in response to respectively input digital signals. A second current cell group of the analog-to-digital converter has a second set of current cells which respectively correspond to the first set of current cells and which individually turn on and off in response to respectively input digital signals such that an on/off state of each of the first set of current cells is opposite an on/off state of each corresponding one of the second set of current cells. The first set of currents cells are connected in parallel between a first power supply voltage and a first node, and the second set of currents cells are connected in parallel between the first node and a second power supply voltage. An output circuit generates an analog signal from either the current flowing from the first current cell group to the first node, or the current flowing from the first node to the second current cell group.
摘要翻译：数模转换器的第一当前单元组具有响应于分别输入的数字信号单独导通和截止的第一组当前单元。模数转换器的第二个当前单元组具有第二组当前单元，它们分别对应于当前单元的第一组，并响应于分别输入的数字信号单独导通和关断，使得开/关第一组当前单元格中的每一个的状态与第二组当前单元格中的每个对应的一个的开/关状态相反。第一组电流单元并联连接在第一电源电压和第一节点之间，并且第二组电流单元在第一节点和第二电源电压之间并联连接。输出电路从从第一当前单元组流向第一节点的电流或从第一节点流向第二当前单元组的电流产生模拟信号。

82. 发明授权

US06195030B1 Method and electronic circuitry for providing a stable digital to analog converter analog output in integrated circuit digital to analog converter applications 有权
标题翻译：用于在集成电路数模转换器应用中提供稳定的数模转换器模拟输出的方法和电子电路
公开(公告)号：US06195030B1
公开(公告)日：2001-02-27
申请号：US09335578
申请日：1999-06-18
申请人： Rogelio Peon , Maarten Visee
发明人： Rogelio Peon , Maarten Visee
IPC分类号： H03M166
CPC分类号： H03M1/1014 , H03M1/742
摘要： A method and electronic circuitry for providing a Digital to Analog converter analog output in Integrated Circuit Digital to Analog Converter applications, said analog output being stable over temperature and supply changes, independent on transistor parameters of a particular chip, and stable for transistor parameter variation from chip to chip. An integrated circuit reference cell is implemented; an internal (secondary) reference quantity determining the analog Digital to Analog Converter (DAC) output is generated; the said internal (secondary) reference quantity for the Digital to Analog converter is referenced to on-chip device specific internal (primary) reference output from the chip in question, and the said chip device specific internal (primary) reference output, is processed further in order to derive a fixed predetermined DAC reference value, that is equal for any chip; and said fixed predetermined DAC reference value is supplied to the digital input of said Digital to Analog converter.
摘要翻译：一种用于在集成电路数模转换器应用中提供数模转换器模拟输出的方法和电子电路，所述模拟输出在温度和电源变化方面是稳定的，独立于特定芯片的晶体管参数，并且对于晶体管参数变化是稳定的芯片到芯片。实现集成电路参考单元; 产生确定模拟数模转换器（DAC）输出的内部（次要）参考量; 用于数模转换器的所述内部（次级）参考数量参考所讨论的芯片的片上器件专用内部（主要）参考输出，并且所述芯片器件特定的内部（主要）参考输出被进一步处理以便导出固定的预定DAC参考值，对于任何芯片是相等的; 并且所述固定的预定DAC参考值被提供给所述数模转换器的数字输入。

83. 发明授权

US6130632A Digitally self-calibrating current-mode D/A converter 失效
标题翻译：数字自校准电流模式D / A转换器
公开(公告)号：US6130632A
公开(公告)日：2000-10-10
申请号：US62157
申请日：1998-04-16
申请人： Ion E. Opris
发明人： Ion E. Opris
IPC分类号： H03M1/10 , H03M1/74
CPC分类号： H03M1/1061 , H03M1/742
摘要： Digital self-calibration of digital-to-digital converters includes an approach to correct for the arbitrary errors in the analog section provided that there are sufficient redundancy in the architecture. The calibration procedure is performed off-line (upon power-up or user request). The digital correction technique avoids the need of a very accurate current mirror or an extra digital-to-analog converter as a standard transfer device.
摘要翻译：数字 - 数字转换器的数字自校准器包括一种纠正模拟部分任意错误的方法，前提是架构中有足够的冗余。校准程序离线执行（上电或用户请求时）。数字校正技术避免了使用非常精确的电流镜或额外的数模转换器作为标准传送装置。

84. 发明授权

US5801653A Current cell of a digital-to-analog converter 失效
标题翻译：数模转换器的当前单元
公开(公告)号：US5801653A
公开(公告)日：1998-09-01
申请号：US728561
申请日：1996-10-10
申请人： Ding-Jeng Liu , Ying-Tzung Wang , Wen-Hsin Cheng
发明人： Ding-Jeng Liu , Ying-Tzung Wang , Wen-Hsin Cheng
IPC分类号： H03M1/66
CPC分类号： H03M1/0863 , H03M1/742
摘要： A current cell for converting a digital signal to an analog current signal is disclosed. The current cell includes a first PMOS transistor which receives the digital signal from a pre-stage processor by the gate. A drain of the first PMOS transistor is grounded. A second PMOS transistor has a source which is connected to the source of the first PMOS transistor, a gate which receives an inverse signal of the digital signal from the pre-stage processor, and a drain for providing the analog current signal. A third PMOS transistor is connected between a voltage source and the source of the first PMOS transistor. The third PMOS transistor has a gate to which a first reference voltage is applied.
摘要翻译：公开了一种用于将数字信号转换为模拟电流信号的电流单元。当前单元包括第一PMOS晶体管，其通过门接收来自前级处理器的数字信号。第一PMOS晶体管的漏极接地。第二PMOS晶体管具有连接到第一PMOS晶体管的源极的源极，接收来自前级处理器的数字信号的反相信号的栅极和用于提供模拟电流信号的漏极。第三PMOS晶体管连接在电压源和第一PMOS晶体管的源极之间。第三PMOS晶体管具有施加第一参考电压的栅极。

85. 发明授权

US5748127A Two cascoded transistor chains biasing DAC current cells 失效
标题翻译：两个级联晶体管链偏置DAC电流单元
公开(公告)号：US5748127A
公开(公告)日：1998-05-05
申请号：US579073
申请日：1995-12-22
申请人： Jaideep Prakash , John Paul Norsworthy , Bruce Andrew Doyle
发明人： Jaideep Prakash , John Paul Norsworthy , Bruce Andrew Doyle
IPC分类号： H03M1/06 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0604 , H03M1/742
摘要： A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion. Additionally, the biasing circuit minimizes noise coupling from ground potential to the D/A convertor output. A reset circuit is also included. This current cell, associated biasing stage, and reset circuit is suitable for applications requirement precise D/A conversions at high speeds.
摘要翻译：用于数模（D / A）转换器电路的精确电流单元被设计为补偿制造工艺变化。电池使用级联晶体管链来控制输出电压并隔离电源电压噪声。外部（芯片外）偏置电流被馈送到八个晶体管的级联偏压串中，其进一步镜像到当前单元本身。偏置方案考虑到芯片中的制造工艺变化，这导致在D / A电路的输出端复制非常精确的电流。当前电池中的电流转向和改善的分流路径使当前电池切换期间的电压摆幅最小化。这允许更快地切换电池，同时最小化由于电压摆动引起的噪声耦合。当前单元还具有相关联的偏置级。该偏置级允许改善当前单元内的匹配，从而提高转换精度。此外，偏置电路最小化从地电位到D / A转换器输出的噪声耦合。还包括复位电路。该电流单元，相关偏置级和复位电路适用于要求高速精确D / A转换的应用。

86. 发明授权

US5703582A DAC with feedback control for current source bias during non-display period 失效
标题翻译： DAC在非显示期间具有用于电流源偏置的反馈控制
公开(公告)号：US5703582A
公开(公告)日：1997-12-30
申请号：US627663
申请日：1996-04-01
申请人： Seiji Koyama , Tohru Nozawa , Asao Terukina , Yasusuke Suzuki
发明人： Seiji Koyama , Tohru Nozawa , Asao Terukina , Yasusuke Suzuki
IPC分类号： H04N9/00 , H03M1/10 , H03M1/74 , H03M1/70
CPC分类号： H03M1/1023 , H03M1/742
摘要： A D/A converter of a current output type desirably compensates for changes in the switching characteristic that arise in each constant current circuit. The D/A converter generates an analog output current that is in response to the level of input digital data and outputs it from an output side by switching each of output currents of a plurality of constant current circuits either to the output side or to a non-output side, in response to the input digital data. The D/A converter performs feedback control, for values of the output currents for the constant current circuits, based on an analog output current at the non-output side during a period when the output currents of all of the constant current circuits are connected to the non-output sides.
摘要翻译：电流输出型的D / A转换器理想地补偿每个恒流电路中产生的开关特性的变化。 D / A转换器产生模拟输出电流，其响应于输入数字数据的电平并且通过将多个恒定电流电路的每个输出电流切换到输出侧或非输出侧而从输出侧输出，输出端，响应输入的数字数据。 D / A转换器根据所有恒流电路的输出电流连接到非输出侧的模拟输出电流，对恒定电流电路的输出电流值进行反馈控制非输出端。

87. 发明授权

US5638073A Method of linearizing variations in the transfer characteristic of a D/A converter, as well as an arrangement and use thereof 失效
标题翻译：线性化D / A转换器的传送特性的变化的方法，以及其布置和用途
公开(公告)号：US5638073A
公开(公告)日：1997-06-10
申请号：US395592
申请日：1995-02-28
申请人： Karlheinz Grotz , Jorg Mayer
发明人： Karlheinz Grotz , Jorg Mayer
IPC分类号： H03M1/10 , H03M1/74 , H03M1/66
CPC分类号： H03M1/1042 , H03M1/742
摘要： A method is provided for linearizing variations in a transfer characteristic of a digital-to-analog (D/A) converter to which a digitized input signal is fed for being converted to an analog output signal. The method includes balancing the D/A converter so that essentially only negative differential variations result in the transfer characteristic at identified locations; determining amplitudes of the negative differential variations; and adding, with an inverse operational sign, the respective amplitudes of the negative differential variations to the input signal of the D/A converter at the respective locations of the variations.
摘要翻译：提供了一种用于线性化数字化模拟（D / A）转换器的转换特性的变化的方法，数字化输入信号被馈送到数模转换器转换为模拟输出信号。该方法包括平衡D / A转换器，使得基本上只有负差分变化导致识别位置处的传输特性; 确定负差分变化的幅度; 并且以相反的操作符号，在变化的各个位置处增加与D / A转换器的输入信号的负差分变化的相应幅度。

88. 发明授权

US5570090A DAC with digitally-programmable gain and sync level generation 失效
标题翻译： DAC具有数字可编程增益和同步电平生成
公开(公告)号：US5570090A
公开(公告)日：1996-10-29
申请号：US247263
申请日：1994-05-23
申请人： Timothy J. Cummins
发明人： Timothy J. Cummins
IPC分类号： H03M1/10 , H03M1/66 , H03M1/74
CPC分类号： H03M1/66 , H03M1/1014 , H03M1/742
摘要： An integrated-circuit (IC) chip formed with a D/A converter (DAC) having a digitally-programmable circuit for setting the full-scale output range of the DAC by controlling its gain. The IC chip further includes analog sync level generator circuitry for driving computer graphics CRTs. The sync level generator circuitry is integrated with the DAC circuitry in such a way that the sync signal levels track changes made to the full-scale operating output range of the DAC and also track with changes in operating conditions such as varying temperature, supply voltage and RSET resistance in the DAC current control circuitry.
摘要翻译：由具有数字可编程电路的D / A转换器（DAC）形成的集成电路（IC）芯片，用于通过控制其增益来设置DAC的满量程输出范围。 IC芯片还包括用于驱动计算机图形CRT的模拟同步电平发生器电路。同步电平发生器电路与DAC电路集成，使得同步信号电平跟踪对DAC的满量程工作输出范围所做的改变，并且还跟踪操作条件的变化，例如变化的温度，电源电压和 DAC电流控制电路中的RSET电阻。

89. 发明授权

US5541598A Current cell for converting a binary value to an analog value 失效
标题翻译：用于将二进制值转换为模拟值的当前单元格
公开(公告)号：US5541598A
公开(公告)日：1996-07-30
申请号：US333973
申请日：1994-11-03
申请人： Behnam Malek-Khosravi
发明人： Behnam Malek-Khosravi
IPC分类号： H03M1/74 , H03K17/041 , H03K19/017 , H03K19/0175 , H03K19/0948 , H03M1/08 , H03M1/66
CPC分类号： H03K17/04106 , H03M1/0863 , H03M1/742
摘要： A digital value represented by binary signals is converted to a corresponding analog value by three (3) current cells, preferably C-MOS p-type, in a digital-to-analog converter (DAC). The three (3) transistors, preferably disposed on an integrated circuit chip, comprise (a) an input switch transistor receiving a digital input signal at its gate, (b) an output transistor providing an output current at its drain and (c) a current bias transistor. The switch and output transistor sources and the bias transistor drain are common. The output transistor gate is biased by a substantially constant voltage. The bias transistor source receives a supply voltage through a bonding pad on an integrated circuit chip and a bond wire extending from the pad to a pin on the chip package lead frame. At low frequencies (e.g. 100 MHz), the wave shape of the output transistor drain current is flat. At increased frequencies (e.g. 225 MHz), the output current has a spike from a supply voltage spike induced in the bond wire as a result of different magnitudes in the bias transistor current when the switch transistor responds to binary signals.
摘要翻译：由二进制信号表示的数字值在数模转换器（DAC）中被三（3）个当前单元，最好是C-MOS p型转换成相应的模拟值。优选地设置在集成电路芯片上的三（3）个晶体管包括（a）在其栅极处接收数字输入信号的输入开关晶体管，（b）在其漏极处提供输出电流的输出晶体管，以及（c）电流偏置晶体管。开关和输出晶体管源极和偏置晶体管漏极是常见的。输出晶体管栅极被基本恒定的电压偏置。偏置晶体管源通过集成电路芯片上的接合焊盘和从焊盘延伸到芯片封装引线框架上的引脚的接合线接收电源电压。在低频（例如100MHz）下，输出晶体管漏极电流的波形是平坦的。在增加的频率（例如225MHz）下，当开关晶体管响应二进制信号时，由于偏置晶体管电流的不同幅度，输出电流具有从接合线中引起的电源电压尖峰的尖峰。

90. 发明授权

US5535174A Random access memory with apparatus for reducing power consumption 失效
公开(公告)号：US5535174A
公开(公告)日：1996-07-09
申请号：US296739
申请日：1994-08-26
申请人： Stephen W. Harston
发明人： Stephen W. Harston
IPC分类号： G11C7/10 , G11C11/417 , H03M1/00 , H03M1/06 , H03M1/74 , G11C13/00
CPC分类号： G11C7/1039 , G11C11/417 , G11C7/1048 , H03M1/002 , H03M1/742
摘要： A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

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