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81. 发明授权

US08842027B2 Analog to digital converter and method for evaluating capacitor weighting of digital-to-analog converter thereof 有权
标题翻译：用于评估其数模转换器的电容器加权的模数转换器和方法
公开(公告)号：US08842027B2
公开(公告)日：2014-09-23
申请号：US13845121
申请日：2013-03-18
申请人： Industrial Technology Research Institute
发明人： Xuan-Lun Huang , Hao-Jen Lin , Jiun-Lang Huang
IPC分类号： H03M1/10
CPC分类号： H03M1/1057 , H03M1/468
摘要： A method for evaluating capacitor weighting of an analog-to-digital (ADC) is provided. An equivalent weighting value of each composed capacitor in each sub-capacitor-array may be obtained by adding the switch device to the ADC which enables each sub-capacitor-array in a digital-to-analog (DAC) to be measured by each other. The ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and successive approximation result of each input signal.
摘要翻译：提供了一种用于评估模数（ADC）的电容器加权的方法。每个子电容器阵列中的每个组合电容器的等效加权值可以通过将开关器件加到ADC来获得，该ADC使数模（DAC）中的每个子电容器阵列彼此测量。 ADC可以通过使用校准的等效加权和每个输入信号的逐次逼近结果来计算并获得正确的数字输出。

82. 发明授权

US08754798B2 High-speed successive-approximation-register analog-to-digital converter and method thereof 有权
标题翻译：高速逐次逼近寄存器模数转换器及其方法
公开(公告)号：US08754798B2
公开(公告)日：2014-06-17
申请号：US13706600
申请日：2012-12-06
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang Lin
IPC分类号： H03M1/12 , H03M1/38 , H03M1/10
CPC分类号： H03M1/38 , H03M1/0692 , H03M1/10 , H03M1/1009 , H03M1/125 , H03M1/40 , H03M1/403 , H03M1/468
摘要： In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data.
摘要翻译：在一个实施例中，SAR（逐次逼近寄存器）ADC（模拟 - 数字转换器）包括：多个电容器，当采样信号被断言时由用于将公共节点连接到接地节点的采样信号控制的开关 ; 由采样信号控制的多个交换网络和包括相应的接地位和相应的数据位的多个控制位，用于将相应电容器的底板连接到模拟输入信号的多个开关网络中的每一个，接地节点，第一参考电压或第二参考电压，这取决于被断言的信号或位; 比较器，用于检测公共节点处的电压的极性，并且当比较信号被断言时，输出二进制判定以及互补的二进制判定; 用于接收二进制判定和互补二进制判定的逻辑门，并输出指示是否容易做出判定的就绪信号; 定时器，用于接收比较信号并输出超时信号; 以及用于接收二进制判定，就绪信号和超时信号并输出采样信号，比较信号，多个控制位和输出数据的SAR逻辑。

83. 发明申请

US20140132430A1 ANALOG-TO-DIGITAL CONVERTER SYSTEM AND METHOD 审中-公开
标题翻译：模拟数字转换器系统和方法
公开(公告)号：US20140132430A1
公开(公告)日：2014-05-15
申请号：US14162559
申请日：2014-01-23
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Jesper STEENSGAARD-MADSEN
IPC分类号： H03M1/20
CPC分类号： H03M1/201 , H03M1/0641 , H03M1/0668 , H03M1/462 , H03M1/468
摘要： An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.
摘要翻译：一种模数转换器（ADC）系统和方法。根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。呈现了几个实施例。

84. 发明申请

US20140118175A1 SUCCESSIVE APPROXIMATION A/D CONVERTER 有权
标题翻译：连续逼近A / D转换器
公开(公告)号：US20140118175A1
公开(公告)日：2014-05-01
申请号：US14059680
申请日：2013-10-22
申请人： Asahi Kasei Microdevices Corporation
发明人： Junya NAKANISHI
IPC分类号： H03M1/36
CPC分类号： H03M1/0678 , H03M1/468
摘要： The successive approximation A/D converter includes: switch groups 105—1 to 105—x each of which is connected to the other end of each corresponding capacitor of capacitors 106—1 to 106—x to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct1; a comparator 104 for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part 107 for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct2 for a predetermined period when a predetermined time has elapsed after the successive comparison.
摘要翻译：逐次逼近A / D转换器包括：开关组105-1至105-x，每个开关组105-1至105-x连接到电容器106-1至106-x的每个相应电容器的另一端，以选择性地将要施加的电容器响应于开关组控制信号Ct1的连续比较; 比较器104，用于基于通过电容器中的开关组选择的每个相应的电容器上的保持电压与定时控制信号CLK同步的预定参考电压VC，连续比较比较电压VSN，以获得根据比较结果判断输出; 以及电压施加部107，用于在连续比较之后经过预定时间时，基于电压形式施加控制信号Ct2，将预定电压施加到预定时间段的比较电压。

85. 发明授权

US08653998B2 D/A conversion circuit, A/D conversion circuit and electronic apparatus 有权
标题翻译： D / A转换电路，A / D转换电路和电子设备
公开(公告)号：US08653998B2
公开(公告)日：2014-02-18
申请号：US13401485
申请日：2012-02-21
申请人： Hideo Haneda , Takemi Yonezawa
发明人： Hideo Haneda , Takemi Yonezawa
IPC分类号： H03M1/66
CPC分类号： H03M1/066 , H03M1/468 , H03M1/687 , H03M1/804 , H03M1/806
摘要： A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.
摘要翻译： AD / A转换电路包括与输出节点连接的第一D / A转换部分，布置在输出节点和第一节点之间的第一串行电容器，与第一D / A转换部分连接的第二D / A转换部分节点和控制电路。第一D / A转换部分包括第一电容器阵列部分和第一开关阵列部分。第二D / A转换部分包括第二电容器阵列部分和第二开关阵列部分。控制电路执行用于动态地改变电容器的分配到第一D / A转换部分的第一开关阵列部分的输入数字数据的各个位的开关控制。

86. 发明授权

US08638248B2 Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter 有权
标题翻译：用于具有电荷再分配数模转换器的逐次逼近模数转换器的独立于输入的自校准方法和装置
公开(公告)号：US08638248B2
公开(公告)日：2014-01-28
申请号：US13269495
申请日：2011-10-07
申请人： Qiong Wu , Kevin Mahooti
发明人： Qiong Wu , Kevin Mahooti
IPC分类号： H03M1/06
CPC分类号： H03M1/1047 , H03M1/1052 , H03M1/462 , H03M1/468
摘要： A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.
摘要翻译：一种用于校正数据采集系统的偏移和线性误差的方法和装置。电荷再分配数字到模拟转换器（CDAC）连接到比较器的一个差分输入端，其比较器的第二输入来自功能CDAC。校准算法内置在数字控制单元中。数字控制单元依次检测偏移和电容器失配误差，将每个误差的校准码存储在校准模式中，并提供与二进制搜索定时同步的输入相关误差校正信号，以调整比较器的差分输入并补偿输入在正常转换期间，非理想函数CDAC的输出存在相关误差。

87. 发明授权

US08604961B1 Ratiometric ADC circuit arrangement 有权
标题翻译：比例ADC电路布置
公开(公告)号：US08604961B1
公开(公告)日：2013-12-10
申请号：US13594918
申请日：2012-08-27
申请人： Peter Bogner , Hubert Rothleitner
发明人： Peter Bogner , Hubert Rothleitner
IPC分类号： H03M1/12
CPC分类号： H03M1/0619 , H03M1/0617 , H03M1/468
摘要： In various embodiments an analog-to-digital converter arrangement is provided, which may include an input terminal configured to receive a signal to be converted; a reference terminal configured to receive a reference signal; a voltage domain specific reference terminal configured to receive a voltage domain specific reference signal; an analog-to-digital converter circuit coupled to the input terminal, the reference terminal, and to the voltage domain specific reference terminal configured to compare the signal to be converted with the voltage domain specific reference signal, thereby generating a first digital comparison signal, and to compare the reference signal with the voltage domain specific reference signal, thereby generating a second digital comparison signal; and a ratiometric circuit configured to determine a digitally converted signal of the signal to be converted using the first digital comparison signal and the second digital comparison signal.
摘要翻译：在各种实施例中，提供了模数转换器装置，其可以包括被配置为接收要转换的信号的输入端子; 参考终端，被配置为接收参考信号; 电压域专用参考端子，被配置为接收电压域专用参考信号; 耦合到输入端子，参考端子和电压域特定参考端子的模数转换器电路，其被配置为将要转换的信号与电压域特定参考信号进行比较，由此产生第一数字比较信号，并将参考信号与电压域专用参考信号进行比较，从而产生第二数字比较信号; 以及比例计电路，被配置为使用第一数字比较信号和第二数字比较信号确定要转换的信号的数字转换信号。

88. 发明授权

US08581770B2 Zero-power sampling SAR ADC circuit and method 有权
标题翻译：零功率采样SAR ADC电路及方法
公开(公告)号：US08581770B2
公开(公告)日：2013-11-12
申请号：US13068192
申请日：2011-05-04
申请人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
发明人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
IPC分类号： H03M1/12
CPC分类号： H03M1/1295 , H03M1/468
摘要： A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
摘要翻译：开关电容器电路（10,32或32A）通过将加法导体（13）的顶板切换到第一参考电压（VSS）而将第一信号（VIN +）采样到第一电容器（C1或CIN1）上，并且将其底板切换到第一信号。将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。在采样之后，第二电容器的顶板耦合到第一电容器的顶板。第二电容器的底板耦合到第一参考电压。第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。开关电容电路可以是SAR，积分器或放大器。

89. 发明授权

US08570205B2 Analog to digital converter with leakage current correction circuit 有权
标题翻译：具有泄漏电流校正电路的模数转换器
公开(公告)号：US08570205B2
公开(公告)日：2013-10-29
申请号：US13363471
申请日：2012-02-01
申请人： Maher Mahmoud Sarraj , Haydar Bilhan
发明人： Maher Mahmoud Sarraj , Haydar Bilhan
IPC分类号： H03M1/40
CPC分类号： H03F3/005 , H03F3/45475 , H03K17/162 , H03K2217/0054 , H03M1/06 , H03M1/468
摘要： An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.
摘要翻译：模数转换器包括泄漏电流校正电路，用于消除采用具有基本上类似于复位开关的形状因子的虚拟PMOS开关的复位开关注入的泄漏电流。运算放大器将比较器感测输入节点的电压复制到虚拟晶体管的漏极，以创建与复位开关相同的工作点。然后重复所产生的漏电流并将其反馈到节点以消除有漏电流。

90. 发明授权

US08531328B2 Analog digital converter 有权
标题翻译：模拟数字转换器
公开(公告)号：US08531328B2
公开(公告)日：2013-09-10
申请号：US13243267
申请日：2011-09-23
申请人： Young-deuk Jeon , Young Kyun Cho , Jaewon Nam , Jong-Kee Kwon
发明人： Young-deuk Jeon , Young Kyun Cho , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/164 , H03M1/468
摘要： Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.
摘要翻译：提供了一种模拟数字转换器（ADC）。 ADC包括：产生电平电压的电容器阵列; 比较器，通过比较电平电压输出比较信号; 以及逻辑电路，其基于所述比较信号确定模拟信号的数字位，其中所述逻辑电路在所述电容器阵列中执行所述模拟信号的采样操作时，确定所述模拟信号的数字位中的至少一个数字位。

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