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1. 发明授权

US08178915B1 Unitary floating-gate electrode with both N-type and P-type gates 有权
标题翻译：具有N型和P型门的单一浮栅电极
公开(公告)号：US08178915B1
公开(公告)日：2012-05-15
申请号：US13070263
申请日：2011-03-23
申请人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
发明人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
IPC分类号： H01L27/108
CPC分类号： H01L21/28273 , H01L27/0805 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且分别包括用作n沟道和p沟道MOS晶体管的栅电极的n型和p型掺杂部分。金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。在模拟浮栅电极的表面处，在浮栅电极的n型和p型掺杂部分邻接的位置处的开口允许在该位置形成硅化物，使p-n结短路。

2. 发明授权

US08581770B2 Zero-power sampling SAR ADC circuit and method 有权
标题翻译：零功率采样SAR ADC电路及方法
公开(公告)号：US08581770B2
公开(公告)日：2013-11-12
申请号：US13068192
申请日：2011-05-04
申请人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
发明人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
IPC分类号： H03M1/12
CPC分类号： H03M1/1295 , H03M1/468
摘要： A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
摘要翻译：开关电容器电路（10,32或32A）通过将加法导体（13）的顶板切换到第一参考电压（VSS）而将第一信号（VIN +）采样到第一电容器（C1或CIN1）上，并且将其底板切换到第一信号。将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。在采样之后，第二电容器的顶板耦合到第一电容器的顶板。第二电容器的底板耦合到第一参考电压。第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。开关电容电路可以是SAR，积分器或放大器。

3. 发明申请

US20120280841A1 Zero-power sampling SAR ADC circuit and method 有权
标题翻译：零功率采样SAR ADC电路及方法
公开(公告)号：US20120280841A1
公开(公告)日：2012-11-08
申请号：US13068192
申请日：2011-05-04
申请人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
发明人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/1295 , H03M1/468
摘要： A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
摘要翻译：开关电容器电路（10,32或32A）通过将加法导体（13）的顶板切换到第一参考电压（VSS）而将第一信号（VIN +）采样到第一电容器（C1或CIN1）上，并且将其底板切换到第一信号。将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。在采样之后，第二电容器的顶板耦合到第一电容器的顶板。第二电容器的底板耦合到第一参考电压。第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。开关电容电路可以是SAR，积分器或放大器。

4. 发明授权

US5550889A Alignment of an x-ray tube focal spot using a deflection coil 失效
标题翻译：使用偏转线圈对x射线管焦点进行对准
公开(公告)号：US5550889A
公开(公告)日：1996-08-27
申请号：US345082
申请日：1994-11-28
申请人： Michael F. Gard , Stephen W. Gravelle , Jiang Hsieh , Quan N. Lu , John W. Newman , Thomas L. Toth , Michael A. Wu
发明人： Michael F. Gard , Stephen W. Gravelle , Jiang Hsieh , Quan N. Lu , John W. Newman , Thomas L. Toth , Michael A. Wu
IPC分类号： H01J35/14 , H01J35/26 , H01J35/30 , H05G1/26 , H05G1/52
CPC分类号： H05G1/52 , H01J35/14 , H01J35/26 , H01J35/30 , H05G1/26
摘要： Precise alignment of the focal spot position on an x-ray CT system is achieved using a deflection coil that produces a magnetic field which acts on the electron beam path in the x-ray tube. A variable current power supply drives the deflection coil and is controlled by input signals to align the focal spot at a static reference position, to correct for focal spot drift between scans, and to wobble the focal spot position during a scan or between scans.
摘要翻译：使用偏转线圈实现x射线CT系统上的焦点位置的精确对准，该偏转线圈产生作用在x射线管中的电子束路径上的磁场。可变电流电源驱动偏转线圈并由输入信号控制，以将焦点对准静态参考位置，以校正扫描之间的焦斑漂移，并在扫描期间或扫描之间摆动焦点位置。

5. 发明授权

US5430784A Computerized tomography imaging using multi-slice detector with selectable slice thickness 失效
标题翻译：计算机断层扫描成像使用多切片检测器与可选切片厚度
公开(公告)号：US5430784A
公开(公告)日：1995-07-04
申请号：US203076
申请日：1994-02-28
申请人： David B. Ribner , Michael A. Wu
发明人： David B. Ribner , Michael A. Wu
IPC分类号： G21K5/02 , A61B6/03 , G01T1/24 , G01T1/29 , G21K1/12
CPC分类号： G01T1/2985 , A61B6/032 , A61B6/4085 , A61B6/5205
摘要： A computerized tomography system includes a detector array made up of a set of detector subelements aligned along a slice thickness direction. A controllable switching matrix selectively interconnects a predetermined number of successive detector subelements to a respective summing amplifier to produce slice-constituent signals which measure a respective slice positioned to pass through a body. Each respective slice having a selectable thickness in a region of interest to be imaged.
摘要翻译：计算机断层摄影系统包括由沿着切片厚度方向排列的一组检测器子元件组成的检测器阵列。可控开关矩阵选择性地将预定数量的连续检测器子元件互连到相应的求和放大器，以产生测量相对于经过身体的切片的切片组成信号。每个相应切片在要成像的感兴趣区域中具有可选择的厚度。

6. 发明授权

US08981445B2 Analog floating-gate memory with N-channel and P-channel MOS transistors 有权
标题翻译：具有N沟道和P沟道MOS晶体管的模拟浮栅存储器
公开(公告)号：US08981445B2
公开(公告)日：2015-03-17
申请号：US13406704
申请日：2012-02-28
申请人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
发明人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
IPC分类号： H01L27/108 , H01L29/66 , H01L21/265 , H01L29/10 , H01L23/522 , H01L27/115 , H01L49/02 , H01L29/94
CPC分类号： H01L29/66825 , H01L21/2652 , H01L23/5223 , H01L27/11517 , H01L27/1156 , H01L28/40 , H01L28/60 , H01L29/105 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

7. 发明授权

US5400385A High voltage power supply for an X-ray tube 失效
标题翻译：用于X射线管的高压电源
公开(公告)号：US5400385A
公开(公告)日：1995-03-21
申请号：US116143
申请日：1993-09-02
申请人： James A. Blake , Jonathan R. Schmidt , Michael A. Wu
发明人： James A. Blake , Jonathan R. Schmidt , Michael A. Wu
IPC分类号： H05G1/20 , H05G1/32 , H05G1/34
CPC分类号： H05G1/20 , H05G1/32
摘要： A supply for a high bias voltage in an X-ray imaging system has an inverter and a voltage multiplier that produce an alternating output voltage in response to control signals. A voltage sensor produces a signal indicating a magnitude of the output voltage. A circuit determines a difference between the sensor signal and a reference signal that specifies a desired magnitude for the output voltage and that difference is integrated to produce an error signal. The error signal preferably is summed with a precondition signal that is an approximation of a nominal value for the signal sum and the summation producing a resultant signal. Another summation device arithmetically combines the resultant signal and the sensor signal with a signal corresponding to a one-hundred percent duty cycle of the inverter operation in order to produce a duty cycle command. An inverter driver generates the inverter control signals that have frequencies defined by the resultant signal and have duty cycles defined by the duty cycle command. A unique state machine is described which generates those control signals.
摘要翻译：用于X射线成像系统中的高偏置电压的电源具有反相器和电压倍增器，其响应于控制信号而产生交流输出电压。电压传感器产生指示输出电压大小的信号。电路确定传感器信号和指定输出电压的期望幅度的参考信号之间的差异，并且该差被积分以产生误差信号。误差信号优选地与作为信号和的标称值的近似值的预处理信号和产生结果信号的求和相加。另一个求和装置将得到的信号和传感器信号与对应于逆变器操作的百分之一百的占空比的信号进行算术组合，以产生占空比指令。逆变器驱动器产生具有由结果信号定义的频率并具有由占空比指令定义的占空比的逆变器控制信号。描述了生成这些控制信号的独特的状态机。

8. 发明授权

US08716083B2 Unitary floating-gate electrode with both N-type and P-type gates 有权
标题翻译：具有N型和P型门的单一浮栅电极
公开(公告)号：US08716083B2
公开(公告)日：2014-05-06
申请号：US13359253
申请日：2012-01-26
申请人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
发明人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/0805 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且分别包括用作n沟道和p沟道MOS晶体管的栅电极的n型和p型掺杂部分。金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。在模拟浮栅电极的表面处，在浮栅电极的n型和p型掺杂部分邻接的位置处的开口允许在该位置形成硅化物，使p-n结短路。

9. 发明申请

US20130221418A1 Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors 有权
标题翻译：模拟浮栅存储器制造工艺实现N沟道和P沟道MOS晶体管
公开(公告)号：US20130221418A1
公开(公告)日：2013-08-29
申请号：US13406704
申请日：2012-02-28
申请人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
发明人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/66825 , H01L21/2652 , H01L23/5223 , H01L27/11517 , H01L27/1156 , H01L28/40 , H01L28/60 , H01L29/105 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

10. 发明申请

US20120244671A1 Unitary Floating-Gate Electrode with Both N-Type and P-Type Gates 有权
标题翻译：具有N型和P型闸门的单一浮栅电极
公开(公告)号：US20120244671A1
公开(公告)日：2012-09-27
申请号：US13359253
申请日：2012-01-26
申请人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
发明人： Allan T. Mitchell , Imran Mahmood Khan , Michael A. Wu
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/0805 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且分别包括用作n沟道和p沟道MOS晶体管的栅电极的n型和p型掺杂部分。金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。在模拟浮栅电极的表面处，在浮栅电极的n型和p型掺杂部分邻接的位置处的开口允许在该位置形成硅化物，使p-n结短路。

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