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81. 发明授权

US07274607B2 Bitline exclusion in verification operation 有权
标题翻译：验证操作中的位线排除
公开(公告)号：US07274607B2
公开(公告)日：2007-09-25
申请号：US11153188
申请日：2005-06-15
申请人： Hendrik Hartono , Aaron Yip , Benjamin Louie
发明人： Hendrik Hartono , Aaron Yip , Benjamin Louie
IPC分类号： G11C7/12
CPC分类号： G11C16/3454 , G11C29/83 , G11C29/832
摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
摘要翻译：用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作失败了

82. 发明授权

US07242601B2 Deterministic addressing of nanoscale devices assembled at sublithographic pitches 有权
标题翻译：以亚光刻间距组装的纳米级器件的确定性寻址
公开(公告)号：US07242601B2
公开(公告)日：2007-07-10
申请号：US10853907
申请日：2004-05-25
申请人： André Dehon , Helia Naeimi
发明人： André Dehon , Helia Naeimi
IPC分类号： G11C6/06 , G11C7/00
CPC分类号： H03K19/1776 , B82Y10/00 , G11C5/063 , G11C8/10 , G11C11/34 , G11C11/54 , G11C29/025 , G11C29/08 , G11C29/76 , G11C29/816 , G11C29/832 , G11C2213/81 , H03K19/17736 , H03K19/17764 , H03K19/1778 , Y10S977/963
摘要： A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.
摘要翻译：一种用于构建和寻址具有已知地址的纳米尺度存储器并且用于容忍在制造或器件操作寿命期间可能出现的缺陷的方法。在施工期间，地址的纳米级电线随机组装。在编程阶段期间，使用其随机地址通过微量输入随机选择纳米线，并且所需的地址码与所选择的纳米尺度线相关联。存储器地址与代码相关联，然后在从/到存储器的读/写操作期间使用已知代码进行选择。

83. 发明申请

US20070147131A1 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US20070147131A1
公开(公告)日：2007-06-28
申请号：US11707341
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

84. 发明申请

US20070147121A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070147121A1
公开(公告)日：2007-06-28
申请号：US11612900
申请日：2006-12-19
申请人： Takuya FUTATSUYAMA
发明人： Takuya FUTATSUYAMA
IPC分类号： G11C16/06 , G11C11/34 , G11C16/04
CPC分类号： G11C8/10 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C29/765 , G11C29/82 , G11C29/832 , G11C2229/723
摘要： According to a nonvolatile semiconductor memory device of the present invention, an address decode section 130 is provided in a block address decode circuit provided in a row decoder of a NAND-type flash memory device. The address decode section 130 has a selected block data storage section 132 composed of a latch circuit, a set section 134, and a reset section 136. The reset section 136 is composed of two nMOS transistors. Thus, defective block data and selected block data to be subjected to a multiple block erasure can be alternately stored in accordance with an operation without causing a complicated circuit structure or an increased chip size.
摘要翻译：根据本发明的非易失性半导体存储器件，在NAND型闪存器件的行解码器中提供的块地址解码电路中提供地址解码部分130。地址译码部分130具有由锁存电路，设定部分134和复位部分136构成的选择的块数据存储部分132。复位部分136由两个nMOS晶体管组成。因此，可以根据操作交替地存储要进行多块擦除的缺陷块数据和所选择的块数据，而不会引起复杂的电路结构或增加的芯片尺寸。

85. 发明申请

US20070147111A1 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US20070147111A1
公开(公告)日：2007-06-28
申请号：US11707343
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

86. 发明申请

US20070127280A1 DETERMINISTIC ADDRESSING OF NANOSCALE DEVICES ASSEMBLED AT SUBLITHOGRAPHIC PITCHES 有权
标题翻译：纳米切片装置的确定性寻址
公开(公告)号：US20070127280A1
公开(公告)日：2007-06-07
申请号：US10853907
申请日：2004-05-25
申请人： Andre DeHon , Helia Naeimi
发明人： Andre DeHon , Helia Naeimi
IPC分类号： G11C5/06
CPC分类号： H03K19/1776 , B82Y10/00 , G11C5/063 , G11C8/10 , G11C11/34 , G11C11/54 , G11C29/025 , G11C29/08 , G11C29/76 , G11C29/816 , G11C29/832 , G11C2213/81 , H03K19/17736 , H03K19/17764 , H03K19/1778 , Y10S977/963
摘要： A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.
摘要翻译：一种用于构建和寻址具有已知地址的纳米尺度存储器并且用于容忍在制造或器件操作寿命期间可能出现的缺陷的方法。在施工期间，地址的纳米级电线随机组装。在编程阶段期间，使用其随机地址通过微量输入随机选择纳米线，并且所需的地址码与所选择的纳米尺度线相关联。存储器地址与代码相关联，然后在从/到存储器的读/写操作期间使用已知代码进行选择。

87. 发明授权

US07180820B2 Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells 有权
标题翻译：包括至少一个字线并且包括多个存储单元的集成半导体存储器
公开(公告)号：US07180820B2
公开(公告)日：2007-02-20
申请号：US11140554
申请日：2005-05-27
申请人： Jörg Kliewer , Herbert Benzinger , Manfred Pröll , Stephan Schröder
发明人： Jörg Kliewer , Herbert Benzinger , Manfred Pröll , Stephan Schröder
IPC分类号： G11C8/00
CPC分类号： G11C11/4085 , G11C29/02 , G11C29/025 , G11C29/83 , G11C29/832 , G11C2029/1202 , H01L27/10891 , H01L27/10897
摘要： An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.
摘要翻译：集成半导体存储器包括至少一个字线和多个存储器单元。每个存储单元具有耦合到字线的选择晶体管。字线驱动器耦合到字线。字线驱动器向字线提供第一电位或第二电势，使得字线由第一电位激活并且被第二电位禁用。无源部件（例如，二极管或电阻器）被耦合在字线和第二电势之间，使得字线通过无源部件以高电阻方式耦合到第二电位。无源元件对于字线和触点连接之间的漏电流是透射的。

88. 发明授权

US07170804B2 Test mode for detecting a floating word line 有权
标题翻译：用于检测浮动字线的测试模式
公开(公告)号：US07170804B2
公开(公告)日：2007-01-30
申请号：US11098998
申请日：2005-04-05
申请人： Norbert Rehm
发明人： Norbert Rehm
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C29/83 , G11C29/832 , G11C2029/1202
摘要： Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of the memory array may be set to an predetermined voltage level (e.g., an intermediate voltage level between VPP and VNWLL). After disconnecting the local word lines on the one side, memory cells on the other side may be tested for read failures, which may indicate floating word lines on the one side.
摘要翻译：提供允许检测存储器阵列中的浮动字线的装置和方法。通过用划分的驱动线驱动来自每侧的本地字线，可以将存储器阵列的一侧上的本地字线设置为预定电压电平（例如，V PP和V V之间的中间电压电平 _{NWLL ）。在断开一侧的本地字线之后，另一侧的存储单元可能被测试读取故障，这可能表示一侧的浮动字线。}

89. 发明授权

US07106627B2 Nonvolatile semiconductor memory device with redundancy and security information circuitry 有权
标题翻译：具有冗余和安全信息电路的非易失性半导体存储器件
公开(公告)号：US07106627B2
公开(公告)日：2006-09-12
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has memory elements selected by an address signal. The second storage area has memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区域具有由地址信号选择的存储元件。第二存储区域具有通过控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

90. 发明授权

US07089375B2 Device and method for configuring a cache tag in accordance with burst length 失效
标题翻译：根据突发长度配置缓存标签的设备和方法
公开(公告)号：US07089375B2
公开(公告)日：2006-08-08
申请号：US11142969
申请日：2005-06-02
申请人： Joseph T. Pawlowski
发明人： Joseph T. Pawlowski
IPC分类号： G06F12/16 , G06F12/02
CPC分类号： G06F12/0802 , G06F12/0879 , G06F2212/601 , G11C11/41 , G11C15/00 , G11C29/816 , G11C29/832 , G11C29/88 , G11C29/883
摘要： In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not functioning properly. In addition, the burst length of the SRAM is increased to reduce the number of tag subarrays necessary for operation of the cache tag so any nonfunctional tag subarrays are no longer necessary. In accordance with the indications from the programmed laser fuses and the increased burst length, logic circuitry disables any nonfunctional tag subarrays, leaving only functional tag subarrays to provide tag functionality for the memory cache. As a result, an SRAM that is typically scrapped as a result of nonfunctional tag subarrays can, instead, be recovered for sale and subsequent use.
摘要翻译：在集成在具有存储器高速缓存的SRAM上的缓存标签中，激光熔丝被编程以指示高速缓存标签中的标签子阵列（如果有的话）不能正常工作。此外，SRAM的突发长度增加以减少高速缓存标签的操作所需的标签子阵列的数量，因此不再需要任何非功能标签子阵列。根据编程激光熔丝的指示和突发长度的增加，逻辑电路禁用任何非功能标签子阵列，只留下功能标签子阵列来为存储器高速缓存提供标签功能。结果，通常由非功能标签子阵列报废的SRAM可以被恢复出售并随后使用。

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