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81. 发明授权

US09508596B2 Processes used in fabricating a metal-insulator-semiconductor field effect transistor 有权
标题翻译：用于制造金属 - 绝缘体 - 半导体场效应晶体管的工艺
公开(公告)号：US09508596B2
公开(公告)日：2016-11-29
申请号：US14311165
申请日：2014-06-20
申请人： Vishay-Siliconix
发明人： Naveen Tipirneni , Deva Pattanayak
IPC分类号： H01L21/8234 , H01L29/78
CPC分类号： H01L21/8234 , H01L29/0619 , H01L29/402 , H01L29/41766 , H01L29/66719 , H01L29/66727 , H01L29/7811 , H01L29/7823
摘要： During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET.
摘要翻译：在制造期间，第二氧化物层设置在结构的第一区域和第二区域上。第二区域包括在第二氧化物层和外延层之间的第一氧化物层。第一区域对应于金属 - 绝缘体 - 半导体场效应晶体管（MISFET）的有源区，并且形成第一类型掺杂源区域，第二类型掺杂物体区域和第二类型掺杂剂注入区域第一个地区。第二区域对应于MISFET的端接区域。在第二区域上形成掩模，并且去除通过间隙暴露的第二氧化物层和第一氧化物层的部分，从而暴露外延层。第二类掺杂剂通过第一和第二氧化物层中的所得开口沉积到外延层中，从而形成用于MISFET的场环。

82. 发明授权

US09496420B2 Molybdenum barrier metal for SiC Schottky diode and process of manufacture 有权
公开(公告)号：US09496420B2
公开(公告)日：2016-11-15
申请号：US11888452
申请日：2007-07-31
申请人： Giovanni Richieri
发明人： Giovanni Richieri
IPC分类号： H01L21/28 , H01L21/44 , H01L29/872 , H01L29/16 , H01L29/47 , H01L29/66 , H01L29/06
摘要： A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.

83. 发明授权

US09437424B2 High mobility power metal-oxide semiconductor field-effect transistors 有权
标题翻译：高迁移率功率金属氧化物半导体场效应晶体管
公开(公告)号：US09437424B2
公开(公告)日：2016-09-06
申请号：US12123664
申请日：2008-05-20
申请人： Deva Pattanayak , Kuo-In Chen , The-Tu Chau
发明人： Deva Pattanayak , Kuo-In Chen , The-Tu Chau
IPC分类号： H01L21/02 , H01L29/739 , H01L29/04 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L21/02433 , H01L21/02516 , H01L21/02609 , H01L29/04 , H01L29/045 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on”resistance of the device.
摘要翻译：高迁移率P沟道功率金属氧化物半导体场效应晶体管。根据本发明的实施例，制造功率MOSFET，使得空穴沿着沿着（110）晶面的反转/累积通道流动或等效，并且电流在[110]中，方向或等同物，当负电位相对于源施加到栅极时。孔的增强的沟道迁移率导致导通状态电阻的沟道部分的减小，从而有利地降低器件的总“导通”电阻。

84. 发明授权

US09425304B2 Transistor structure with improved unclamped inductive switching immunity 有权
标题翻译：具有改进的非钳位感应开关抗扰度的晶体管结构
公开(公告)号：US09425304B2
公开(公告)日：2016-08-23
申请号：US14465697
申请日：2014-08-21
申请人： Vishay-Siliconix
发明人： Wenjie Zhang , Madhur Bobde , Qufei Chen , Kyle Terrill
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/40
CPC分类号： H01L29/781 , H01L21/26586 , H01L29/0623 , H01L29/0626 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4175 , H01L29/41766 , H01L29/66492 , H01L29/66659 , H01L29/66696 , H01L29/66712 , H01L29/7835
摘要： A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.
摘要翻译：横向扩散金属氧化物半导体（LDMOS）晶体管结构，具有改进的非钳位感应开关抗扰性。 LDMOS包括基底和邻近的第一导电类型的外延层。栅极结构在外延层之上。第二导电类型的漏极区域和源极区域都在外延层内。在源极和漏极区域之间形成沟道并且布置在栅极结构的下方。第一导电类型的主体结构至少部分地形成在栅极结构下方并且在源极区域下方横向延伸，其中外延层比主体结构少掺杂。导电沟槽状馈通元件穿过外延层并接触衬底和源极区域。 LDMOS包括形成在源区域下方并且与所述主体结构和所述沟槽状馈通元件横向相邻并与之接触的第一导电类型的桶区域。

85. 发明授权

US09412880B2 Schottky diode with improved surge capability 有权
标题翻译：具有改善浪涌能力的肖特基二极管
公开(公告)号：US09412880B2
公开(公告)日：2016-08-09
申请号：US12903077
申请日：2010-10-12
申请人： Rossano Carta , Luigi Merlin , Laura Bellemo
发明人： Rossano Carta , Luigi Merlin , Laura Bellemo
IPC分类号： H01L23/48 , H01L29/872 , H01L23/495 , H01L29/06 , H01L29/16
CPC分类号： H01L29/872 , H01L23/49562 , H01L29/0619 , H01L29/1608 , H01L2224/26145 , H01L2224/32245 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/00
摘要： An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package. This produces a substantial increase in the surge current capability of the device.
摘要翻译：安装SiC肖特基二极管管芯或Si肖特基二极管管芯，其外延阳极表面连接到器件封装中最佳的散热器表面。这将大大增加器件的浪涌电流能力。

86. 发明授权

US09412833B2 Narrow semiconductor trench structure 有权
标题翻译：窄半导体沟槽结构
公开(公告)号：US09412833B2
公开(公告)日：2016-08-09
申请号：US12030809
申请日：2008-02-13
申请人： The-Tu Chau , Hoang Le , Kuo-In Chen
发明人： The-Tu Chau , Hoang Le , Kuo-In Chen
IPC分类号： H01L29/66
CPC分类号： H01L29/66181
摘要： Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.
摘要翻译：窄半导体沟槽结构的系统和方法。在第一种方法实施例中，形成窄沟槽的方法包括在衬底上形成绝缘材料的第一层，并通过第一绝缘材料层形成沟槽并进入衬底。在第一层上形成第二绝缘材料，并且在沟槽的暴露部分上形成第二绝缘材料，并且第二绝缘材料从绝缘材料的第一层和沟槽的底部移除。沟槽填充有外延材料，并且去除第一绝缘材料层。通过去除第二绝缘材料的剩余部分形成窄沟槽。

87. 发明授权

US09040356B2 Semiconductor including cup-shaped leadframe packaging techniques 有权
标题翻译：半导体包括杯形引线框封装技术
公开(公告)号：US09040356B2
公开(公告)日：2015-05-26
申请号：US12487666
申请日：2009-06-19
申请人： Mike Chang , King Owyang , Yueh-Se Ho , Mohammed Kasem , Lixiong Luo , Wei-Bing Chu
发明人： Mike Chang , King Owyang , Yueh-Se Ho , Mohammed Kasem , Lixiong Luo , Wei-Bing Chu
IPC分类号： H01L21/50 , H01L23/495 , H01L23/31 , H01L23/544
CPC分类号： H01L23/49562 , H01L23/3107 , H01L23/544 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.
摘要翻译：半导体封装包括杯形并保持半导体管芯的引线框架。引线框架与裸片的一侧上的端子电接触，并且引线框架的引线以这样的方式弯曲，使得引线的一部分与管芯的另一侧共面，其还包含一个或多个端子。在引线框架和模具周围形成塑料胶囊。

88. 发明申请

US20140264804A1 STACK DIE PACKAGE 有权
标题翻译：堆叠包装
公开(公告)号：US20140264804A1
公开(公告)日：2014-09-18
申请号：US13829623
申请日：2013-03-14
申请人： VISHAY-SILICONIX
发明人： Kyle TERRILL , Frank KUO , Sen MAO
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L21/561 , H01L23/051 , H01L23/49513 , H01L23/4952 , H01L23/49541 , H01L23/49568 , H01L24/34 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/73 , H01L24/97 , H01L2224/371 , H01L2224/37147 , H01L2224/3754 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48465 , H01L2224/49111 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die.
摘要翻译：在一个实施例中，堆叠管芯封装可以包括引线框架和包括位于第一管芯的第一表面上的栅极和源极的第一管芯和位于第一管芯的第二表面上的漏极，与第一个表面相对。栅极和源极被倒装芯片耦合到引线框架。堆叠管芯封装可以包括第二管芯，其包括位于第二管芯的第一表面上的栅极和漏极，以及位于第二管芯的与第一表面相对的第二表面上的源极。第二管芯的源极面向第一管芯的漏极。

89. 发明申请

US20140235023A1 TRENCH METAL OXIDE SEMICONDUCTOR WITH RECESSED TRENCH MATERIAL AND REMOTE CONTACTS 有权
标题翻译：具有拉伸材料和远程接触的TRENCH金属氧化物半导体
公开(公告)号：US20140235023A1
公开(公告)日：2014-08-21
申请号：US13728997
申请日：2012-12-27
申请人： VISHAY-SILICONIX
发明人： Deva N. Pattanayak , Kyle Terrill , Sharon Shi , Misha Lee , Yuming Bai , Kam Lui , Kuo-in Chen
IPC分类号： H01L27/07 , H01L29/66
CPC分类号： H01L27/0727 , H01L29/4238 , H01L29/456 , H01L29/66143 , H01L29/66477 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.
摘要翻译：与沟槽金属氧化物半导体（MOS）势垒肖特基（TMBS）器件的多晶硅区域以及MOS场效应晶体管（MOSFET）部分的多晶硅区域和单片集成TMBS中的TMBS部分的远程触点和 MOSFET（SKYFET）器件。多晶硅相对于相邻的台面凹陷。源极金属与TMBS部分的多晶硅区域的接触是通过将多晶硅延伸到TMBS部分的有源区域之外来实现的。器件结构的这种改变减轻了在接触步骤之前从TMBS部分的多晶硅和硅台面区域中去除所有氧化物的需要。因此，避免了接触金属侵入到TMBS器件或SKYFET器件中的沟槽的侧壁中。

90. 发明授权

US08735992B2 Power switch with active snubber 有权
标题翻译：带主动缓冲器的电源开关
公开(公告)号：US08735992B2
公开(公告)日：2014-05-27
申请号：US12829247
申请日：2010-07-01
申请人： Kyle Terrill
发明人： Kyle Terrill
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L27/0207 , H01L27/088 , H02M3/1588 , H02M2001/342 , H03K17/162 , Y02B70/1466 , Y02B70/1491
摘要： A power switch with active snubber. In accordance with a first embodiment, an electronic circuit includes a first power semiconductor device and a second power semiconductor device coupled to the first power semiconductor device. The second power semiconductor device is configured to oppose ringing of the first power semiconductor device.
摘要翻译：具有主动缓冲器的电源开关。根据第一实施例，电子电路包括耦合到第一功率半导体器件的第一功率半导体器件和第二功率半导体器件。第二功率半导体器件被配置为抵抗第一功率半导体器件的振铃。

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