专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US5658695A Method for fabricating phase shift mask comprising the use of a second photoshield layer as a sidewall 失效
标题翻译：用于制造相移掩模的方法，其包括使用第二光致遮蔽层作为侧壁
公开(公告)号：US5658695A
公开(公告)日：1997-08-19
申请号：US463244
申请日：1995-06-05
申请人： Yong Kyoo Choi
发明人： Yong Kyoo Choi
IPC分类号： H01L21/027 , G03F1/00 , G03F1/26 , G03F1/30 , G03F9/00
CPC分类号： G03F1/30 , G03F1/26 , G03F1/36
摘要： A method is provided for fabricating a phase shift mask of the out rigger sub-resolution type capable of accurately fabricating an ultra-fine semiconductor circuit. The method includes the steps of depositing a first photoshield metal layer and a first phase shift material layer over a transparent substrate, defining a transmission region for forming an actual pattern and a sub-pattern region for the transmission region, and removing portions of the photoshield metal layer and phase shift material layer disposed at the defined regions, depositing a second phase shift material layer over the resulting structure, and selectively etching back the second phase shift material layer to form phase shift material side walls, depositing over the resulting structure a photoresist film, and etching back the optional material layer such that both the first and second phase shift material layers are sufficiently exposed at their upper surfaces, etching back the first and second phase shift material layers such that they are flush with the first photoshield metal layer to form a phase shift layer at the sub-pattern region, and depositing a second photoshield material layer over the resulting structure, and etching back the second photoshield material layer to form second photoshield material side walls on the phase shift layer side walls.
摘要翻译：提供了一种用于制造能够精确地制造超精细半导体电路的输出装置子分解型的相移掩模的方法。该方法包括以下步骤：在透明基板上沉积第一照相场金属层和第一相移材料层，限定用于形成实际图案的透射区域和用于透射区域的子图案区域，以及去除光罩的部分金属层和相移材料层设置在限定的区域上，在所得结构上沉积第二相移材料层，并且选择性地回蚀第二相移材料层以形成相移材料侧壁，在所得结构上沉积光致抗蚀剂膜，并且蚀刻回可选材料层，使得第一相移材料层和第二相移材料层在其上表面充分暴露，对第一和第二相移材料层进行回蚀，使得它们与第一照相场金属层齐平，在子图案区域形成相移层，并沉积第二个遮光罩ma 在所得到的结构上方，并且蚀刻回第二照片保护层材料层，以在相移层侧壁上形成第二遮光材料侧壁。

82. 发明授权

US5646052A Isolation region structure of semiconductor device and method for making 失效
标题翻译：半导体器件的隔离区结构及其制造方法
公开(公告)号：US5646052A
公开(公告)日：1997-07-08
申请号：US633002
申请日：1996-04-16
申请人： Chang Jae Lee
发明人： Chang Jae Lee
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/76202 , H01L21/76235 , H01L21/763
摘要： A method of forming a semiconductor device by concurrently forming both single-trenched small field regions and double-trench-extension large field regions, and the device so formed. The method includes: forming an insulating layer on a substrate; forming a mask layer on the insulating layer to cover only active regions such that small field regions and large field regions are left uncovered by the mask layer; increasing a thickness of the insulating layer in each field region in proportion to the width of that field region; removing all of the insulating layer in the small field regions while removing only some of the insulating layer in the large field regions so that, in width cross-section, the large field regions have an exposed substrate narrow edge-area that borders both sides of a remaining portion of the insulating layer; forming trenches in the substrate corresponding in location to the exposed substrate areas such that an intermediate-width trench is created in each small field region and such that a wide trench, having two trench-deepening extensions, is created in each large field region; putting conductive material into the trenches such that the trench-deepening extensions are filled completely and the intermediate-width trenches are at least partially filled; and converting a portion of the conductive material into an insulating cap.
摘要翻译：通过同时形成单沟槽小场区域和双沟槽扩展大场区域形成半导体器件的方法以及如此形成的器件。该方法包括：在基板上形成绝缘层; 在绝缘层上形成掩模层以仅覆盖有源区域，使得小场区域和大场区域被掩模层覆盖; 在每个场区域中增加与该场区域的宽度成比例的绝缘层的厚度; 去除小场区域中的所有绝缘层，同时仅去除大场区域中的一些绝缘层，使得在宽截面中，大场区域具有暴露的基板窄边缘区域绝缘层的剩余部分; 在衬底中形成相应于暴露的衬底区域的衬底中的沟槽，使得在每个小场区域中形成中间宽度沟槽，并且使得在每个大场区域中形成具有两个沟槽深化延伸部的宽沟槽; 将导电材料放入沟槽中，使得沟槽加深延伸部完全填充并且中间宽度沟槽至少部分地被填充; 以及将导电材料的一部分转换成绝缘帽。

83. 发明授权

US5644169A Mold and method for manufacturing a package for a semiconductor chip and the package manufactured thereby 失效
标题翻译：用于制造用于半导体芯片的封装件的模具和方法以及由此制造的封装
公开(公告)号：US5644169A
公开(公告)日：1997-07-01
申请号：US624204
申请日：1996-04-03
申请人： Heung Sup Chun
发明人： Heung Sup Chun
IPC分类号： B29C45/02 , B29C45/26 , B29L31/34 , H01L21/56 , H01L31/02 , H01L23/28
CPC分类号： H01L21/565 , H01L2224/48227 , H01L2924/01078 , H01L2924/01079
摘要： A mold and a method for manufacturing a semiconductor package and the semiconductor package manufactured thereby.The semiconductor package includes a chip attached to a paddle of a lead frame. And with electrically connecting the chip and inner leads of lead frame with a metal wire, a semi-finished product having electric connections is molded by using molding dies having an extrusion in a cavity for providing an opening on an upper portion of a light receiving region of the chip, and a transparent lid is provided on the upper portion of the opening of the semiconductor package.With the invention being able to provide an excellent resin semiconductor package and improved manufacturing processes, thereby reducing the manufacturing cost, enhancing a productivity and making a manufacturing process simpler.
摘要翻译：一种用于制造半导体封装的模具和方法以及由此制造的半导体封装。半导体封装包括附接到引线框的桨的芯片。并且通过用金属线将引线框架的芯片和内部引线电连接，具有电连接的半成品通过使用在空腔中具有挤出的模具来模制，以在光接收区域的上部提供开口并且在半导体封装的开口的上部设置透明盖。通过本发明能够提供优异的树脂半导体封装和改进的制造工艺，从而降低制造成本，提高生产率并使制造工艺更简单。

84. 发明授权

US5643829A Method for the fabrication of multilayer electroluminescence device 失效
标题翻译：多层电致发光器件的制造方法
公开(公告)号：US5643829A
公开(公告)日：1997-07-01
申请号：US355777
申请日：1994-12-14
申请人： Hai Yong Kang
发明人： Hai Yong Kang
IPC分类号： C09K11/56 , H05B33/10 , H05B33/12 , H05B33/14
CPC分类号： H05B33/10 , C09K11/567 , H05B33/14
摘要： There is provided a method for the fabrication of multilayer electroluminescence device, comprising the steps of: forming a lower electrode with a predetermined pattern on a substrate: forming a first insulation layer on the lower electrode atop the substrate; forming a multiply luminescent layer consisting of CaS and SrS on the first insulation layer at the same temperature with that for the first insulation layer; forming a second insulation film on the luminescent layer; and forming an upper electrode with a predetermined on the second insulation layer.In the multiply luminescent layer, a plurality of CaS plies and a plurality of SrS plies are formed in such a way that the CaS plies and the SrS plies alternate with each other and the outmost upper and lower plies are formed of CaS.The constituent substances for the multiply luminescent layer, CaS and SrS, can be deposited at the same temperature and have similar lattice constants which can lead to a matched interface between the CaS and SrS plies. By virtue of these advantages, stresses imposed on the interface, including thermal stress, can be significantly reduced.In addition, the matched interface makes electrons be accelerated with large energy, so that the fabricated multilayer luminescence device may show good quality.
摘要翻译：提供了一种制造多层电致发光器件的方法，包括以下步骤：在衬底上形成具有预定图案的下电极：在衬底顶部的下电极上形成第一绝缘层; 在与第一绝缘层相同的温度下，在第一绝缘层上形成由CaS和SrS组成的多发光层; 在发光层上形成第二绝缘膜; 以及在所述第二绝缘层上形成预定的上电极。在多发光层中，以CaS层和SrS层彼此交替形成多个CaS层和多个SrS层，并且最外层和下层由CaS形成。用于多发光层CaS和SrS的组成物质可以在相同的温度下沉积并具有相似的晶格常数，这可以导致CaS和SrS层之间的匹配界面。由于这些优点，可以显着地减少施加在界面上的应力，包括热应力。此外，匹配的界面使电子以大的能量加速，使得制造的多层发光器件可以显示出良好的质量。

85. 发明授权

US5637891A Charge coupled device having different insulators 失效
标题翻译：电荷耦合器件具有不同的绝缘子
公开(公告)号：US5637891A
公开(公告)日：1997-06-10
申请号：US706972
申请日：1996-09-03
申请人： Kyung S. Lee
发明人： Kyung S. Lee
IPC分类号： H01L27/148 , H01L29/423
CPC分类号： H01L27/148 , H01L29/42396
摘要： A charged coupled device structure (CCD) and a method for fabricating the CCD structure, which induces a maximum potential distribution difference by utilizing gate insulation films having different physical properties. The charged coupled device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a plurality of first electrodes spaced at fixed intervals over the first insulation layer, a second insulation layer formed only between the plurality of first electrodes and the first insulation layer, a third insulation layer formed over the entire exposed surface of the first electrodes and the first insulation layer, and a plurality of second electrodes formed only on the surface area corresponding to spaces between the plurality of first electrodes. This gate insulation layers having different physical properties induces a maximum potential distribution difference in a semiconductor substrate with a dielectric constant difference between the insulation layers.
摘要翻译：电荷耦合器件结构（CCD）和用于制造CCD结构的方法，其通过利用具有不同物理性质的栅极绝缘膜来诱导最大电位分布差异。所述带电耦合器件包括半导体衬底，形成在所述半导体衬底上的第一绝缘层，在所述第一绝缘层上以固定间隔隔开的多个第一电极，仅在所述多个第一电极和所述第一绝缘层之间形成的第二绝缘层形成在第一电极和第一绝缘层的整个暴露表面上的第三绝缘层，以及仅形成在对应于多个第一电极之间的空间的表面区域上的多个第二电极。具有不同物理性质的栅极绝缘层在绝缘层之间的介电常数差异引起半导体衬底中的最大电位分布差异。

86. 发明授权

US5619336A Recording apparatus and method for video cassette recorder having snow noise removing function 失效
标题翻译：具有除雪功能的录像机的记录装置和方法
公开(公告)号：US5619336A
公开(公告)日：1997-04-08
申请号：US353282
申请日：1994-12-05
申请人： Ye T. Kim
发明人： Ye T. Kim
IPC分类号： H04N5/7826 , G11B5/027 , G11B15/02 , G11B19/02 , G11B27/36 , H04N5/44 , H04N5/782 , H04N5/76
CPC分类号： G11B27/36 , G11B19/02 , H04N5/44 , H04N5/782
摘要： Recording apparatus and method for a video cassette recorder having a snow noise removing function. The recording apparatus comprises a tuner for tuning a television broadcasting signal received through an antenna to a channel desired by the user, a signal processor for separating a vertical synchronous signal, a video signal and an audio signal from the television broadcasting signal tuned by the tuner, a vertical synchronous signal counting circuit for counting the number of pulses of the vertical synchronous signal from the signal processor, a system controller for discriminating a received state of the television broadcasting signal in response to the vertical synchronous signal from the signal processor and a plurality of output signals from the vertical synchronous signal counting circuit and determining an operating mode of the video cassette recorder in accordance with the discriminated result, and a servo controller for controlling a head dram and a capstan under control of the system controller to record the video and audio signals from the signal processor on a magnetic tape. According to the invention, if the reception of the television broadcasting signal is broken off in a recording operation, a broken-off signal portion is not recorded and only a normal signal portion is selectively recorded.
摘要翻译：具有除雪功能的录像机的记录装置和方法。记录装置包括调谐器，用于将通过天线接收的电视广播信号调谐到用户期望的频道，用于从调谐器调谐的电视广播信号中分离垂直同步信号，视频信号和音频信号的信号处理器，用于对来自信号处理器的垂直同步信号的脉冲数进行计数的垂直同步信号计数电路，用于根据来自信号处理器的垂直同步信号鉴别电视广播信号的接收状态的系统控制器，以及多个来自垂直同步信号计数电路的输出信号和根据鉴别结果确定录像机的操作模式;以及伺服控制器，用于在系统控制器的控制下控制头灯和绞盘以记录视频和来自信号处理器的音频信号在磁性ta上 pe。根据本发明，如果在记录操作中中断电视广播信号的接收，则不记录断开信号部分，并且仅选择性地记录正常信号部分。

87. 发明授权

US5612546A Thin film transistor structure 失效
标题翻译：薄膜晶体管结构
公开(公告)号：US5612546A
公开(公告)日：1997-03-18
申请号：US379300
申请日：1995-01-27
申请人： Jong M. Choi , Chang R. Kim
发明人： Jong M. Choi , Chang R. Kim
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/78696 , H01L29/6675 , H01L29/66765 , H01L29/66787
摘要： A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.
摘要翻译：一种适用于SRAM存储单元的薄膜晶体管的结构和制造方法。薄膜晶体管结构包括形成为具有沟槽的栅极电极，形成在栅电极上的栅极绝缘膜，形成在栅电极的沟槽中的半导体层以及形成在半导体层的相对侧上的杂质区域。薄膜晶体管的制造方法包括：在绝缘基板上依次形成栅极电极和栅极绝缘膜，使其具有凹槽，在沟槽的一部分的栅极绝缘膜上形成半导体层，形成源极/ 通过选择性地将杂质离子注入到半导体层的相对侧中的漏极杂质区域。

88. 发明授权

US5607865A Structure and fabrication method for a thin film transistor 失效
标题翻译：薄膜晶体管的结构和制造方法
公开(公告)号：US5607865A
公开(公告)日：1997-03-04
申请号：US381425
申请日：1995-01-27
申请人： Jong M. Choi , Jong K. Kim
发明人： Jong M. Choi , Jong K. Kim
IPC分类号： H01L21/336 , H01L29/786 , H01L29/06 , H01L21/265
CPC分类号： H01L29/7854 , H01L29/66795
摘要： A structure and fabrication method for a thin film transistor which is suitable for an SRAM memory cell. The thin film transistor structure includes an insulating substrate and a semiconductor layer formed as a wall on the insulation substrate. A gate insulation film is formed on the semiconductor layer and over the entire surface of the insulation substrate. A gate electrode formed on the gate insulation film at the center part of the semiconductor layer. Impurity regions are formed in the semiconductor layer on both sides of the gate electrode.
摘要翻译：一种适用于SRAM存储单元的薄膜晶体管的结构和制造方法。薄膜晶体管结构包括绝缘基板和在绝缘基板上形成为壁的半导体层。在半导体层上和绝缘基板的整个表面上形成栅极绝缘膜。形成在半导体层中心部分的栅极绝缘膜上的栅电极。杂质区形成在栅电极两侧的半导体层中。

89. 发明授权

US5606290A Phase locked loop circuit having lock holder 失效
标题翻译：具有锁定架的锁相环电路
公开(公告)号：US5606290A
公开(公告)日：1997-02-25
申请号：US362314
申请日：1994-12-22
申请人： Dai S. Pang
发明人： Dai S. Pang
IPC分类号： H03L7/18 , H03L7/00 , H03L7/08 , H03L7/089 , H03L7/095 , H03L7/14 , H03L7/183
CPC分类号： H03L7/183 , H03L7/0891 , H03L7/095 , H03L7/14 , H03L2207/18 , Y10S331/02
摘要： A phase locked loop circuit comprising a reference counter, a programmable counter, a phase detector and a lock detector. The phase locked circuit further comprises a lock enable unit for controlling a voltage pump under control of the phase detector, a channel selector for selecting a desired channel according to a user's selection, a lock holder for holding a locked state in response to an output signal from the channel selector and a lock signal from the lock detector, a refresh clock generator for generating a refresh clock signal in response to an output signal from the reference counter, a NAND gate for NANDing an output signal from the lock holder and the refresh clock signal from the refresh clock generator and outputting the resultant signal to the lock enable unit, first and second inverters for inverting the output signal from the NAND gate, respectively, a first transistor for passing the reference signal to a ground terminal in response to an output signal from the first inverter, and a second transistor for passing the voltage controlled oscillating signal to the ground terminal in response to an output signal from the second inverter.
摘要翻译：一种锁相环电路，包括参考计数器，可编程计数器，相位检测器和锁定检测器。所述锁相电路还包括用于在所述相位检测器的控制下控制电压泵的锁定使能单元，用于根据用户选择来选择期望信道的信道选择器，用于响应于输出信号保持锁定状态的锁定保持器来自频道选择器和来自锁定检测器的锁定信号，用于响应于来自参考计数器的输出信号产生刷新时钟信号的刷新时钟发生器，用于将来自锁定保持器的输出信号与刷新时钟来自刷新时钟发生器的信号，并将所得到的信号输出到锁定使能单元，第一和第二反相器分别反相来自与非门的输出信号，第一晶体管用于响应于输出将参考信号传递到接地端子来自第一反相器的信号，以及用于响应地将受压振荡信号传递到接地端的第二晶体管到来自第二反相器的输出信号。

90. 发明授权

US5579315A Heartbeat collision prevention circuit and method 失效
标题翻译：心跳碰撞防止电路及方法
公开(公告)号：US5579315A
公开(公告)日：1996-11-26
申请号：US369457
申请日：1995-01-06
申请人： Hyung L. Lyu , Dong H. Lee
发明人： Hyung L. Lyu , Dong H. Lee
IPC分类号： G06F13/00 , G06F13/376 , H04L12/413 , H04L12/407
CPC分类号： H04L12/40013 , G06F13/376
摘要： Heartbeat collision prevention circuit and method in a network in which a plurality of stations are connected to data and heartbeat lines. The heartbeat collision prevention circuit comprises a first delay element for delaying a clock signal, an OR gate for ORing an output signal from the first delay element and the heartbeat signal, an edge detector for detecting an edge of an output signal from the OR gate, a shift register for loading data from a central processing unit and shifting the laded data in response to an output signal from the edge detector, a second delay element being enabled in response to the output signal from the edge detector to delay the clock signal, an AND gate for ANDing an output signal from the second delay element and an enable signal, a slot time counter being enabled in response to the output signal from the edge detector to count an output signal from the AND gate, a signal operation unit for logically combining a plurality of output signals from the slot time counter and a plurality of output signals from the shift register and outputting the resultant signal as a slot time, and a reset unit for logically combining an output signal from the signal operation unit and the output signal from the edge detector and outputting the resultant signal as a reset signal to the slot time counter.
摘要翻译：网络中的心跳碰撞防止电路和方法，其中多个站连接到数据和心跳线。心跳碰撞防止电路包括用于延迟时钟信号的第一延迟元件，用于对来自第一延迟元件的输出信号进行和操作的或门和心跳信号的边缘检测器，用于检测来自或门的输出信号的边沿，移位寄存器，用于从中央处理单元加载数据，并响应于来自边缘检测器的输出信号移位加载的数据;第二延迟元件响应于来自边缘检测器的输出信号被使能以延迟时钟信号; AND门，用于对来自第二延迟元件的输出信号进行AND运算和使能信号，时隙时间计数器响应于来自边缘检测器的输出信号被使能以对来自与门的输出信号进行计数;信号操作单元，用于逻辑组合来自时隙时间计数器的多个输出信号和来自移位寄存器的多个输出信号，并将所得到的信号作为时隙时间输出，并且复位单元用于逻辑地组合来自信号操作单元的输出信号和来自边缘检测器的输出信号，并将结果信号作为复位信号输出到时隙计时器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式